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VT6508 の電気的特性と機能

VT6508のメーカーはVIAです、この部品の機能は「8 RMII PORTS OF 10/100BASE-T/TX ETHERNET SWITCH CONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 VT6508
部品説明 8 RMII PORTS OF 10/100BASE-T/TX ETHERNET SWITCH CONTROLLER
メーカ VIA
ロゴ VIA ロゴ 




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VT6508 Datasheet, VT6508 PDF,ピン配置, 機能
VIA Technologies, Inc.
Preliminary VT6508 Datasheet
VT6508
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8 RMII PORTS OF 10/100BASE-T/TX
ETHERNET SWITCH CONTROLLER
REVISION ‘D’ DATASHEET
(Preliminary)
ISSUE 1: Nov 23, 1999
VIA Technologies, Inc.
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VT6508 pdf, ピン配列
VIA Technologies, Inc.
Preliminary VT6508 Datasheet
TABLE OF CONTENTS
TABLE OF CONTENTS ................................................................................................................................ 3
FIGURES AND TABLES ............................................................................................................................... 4
REVERSION HISTORY ................................................................................................................................ 5
FEATURES ................................................................................................................................................ 6
BLOCK DIAGRAM...................................................................................................................................... 9
FIGURE 1: FUNCTION BLOCK DIAGRAM OF VT6508. (NOTE THAT SOME INTERFACE
SIGNALS ARE ONLY AVAILABLE IN VT6509 OF 208-PIN PQFP PACKAGE.).............................. 9
PINOUT DIAGRAM................................................................................................................................... 10
FIGURE 2: PINOUT DIAGRAM OF VT6508. ...................................................................................... 10
PIN DESCRIPTIONS.................................................................................................................................. 11
DEFINITION OF VT6508B STRAPPING PINS .............................................................................................. 12
Pin.................................................................................................................................................... 12
SRAM TYPE: .................................................................................................................................... 12
SECTION I FUNCTIONAL DESCRIPTIONS...................................................................................... 15
1 GENERAL DESCRIPTION ...................................................................................................................... 15
2 THE VIA ETHER SWITCH ARCHITECTURE............................................................................................ 15
2.1 Switch initialization procedures .................................................................................................. 15
2.2 Packet Switching Flow ................................................................................................................ 16
2.3 PACKET BUFFERS AND FORWARDING TABLE ...................................................................................... 16
FIGURE 3. SRAM MEMORY LAYOUT............................................................................................... 17
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FIGURE 4. DATA STRUCTURE OF FORWARDING TABLE SLOT................................................ 17
FIGURE 5. DATA STRUCTURE OF EMBEDDED LINK NODE. ...................................................... 17
2.3 RMII INTERFACE.............................................................................................................................. 19
2.3 MANAGEMENT INTERFACE AND AUTO NEGOTIATION ......................................................................... 19
2.4 FLOW CONTROL ............................................................................................................................... 21
FIGURE 6. XON/XOFF WINDOW CONCEPT..................................................................................... 23
2.5 BROADCAST STORM FILTERING ......................................................................................................... 27
2.6 SERIAL EEPROM INTERFACE AND CONFIGURATION COMMANDS ........................................................ 27
2.7 TRUNKING....................................................................................................................................... 28
3 THE VT6508 SRAM ADDRESS MAPPING TABLE ............................................................... 30
SECTION II REGISTER MAP............................................................................................................... 31
1. REGISTERS TABLE ............................................................................................................................. 31
SECTION III ELECTRICAL SPECIFICATIONS................................................................................. 45
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 45
DC CHARACTERISTICS............................................................................................................................ 45
AC CHARACTERISTICS............................................................................................................................ 46
PACKAGE MECHANICAL SPECIFICATIONS ................................................................................................. 48
3
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3Pages


VT6508 電子部品, 半導体
VIA Technologies, Inc.
Preliminary VT6508 Datasheet
FEATURES
l Single chip 8 ports 10/100Mbps Ethernet switch controller
- Highly integrated single chip shared memory switch engine
- Supports 8 RMII (Reduced Media Independent Interface) ports
- Non-blocking layer 2 switch, 148,810 packets/sec on each 100Mbps Ethernet port
l Media Access Control (MAC)
- Dual 64-byte FIFO’s per port for receiving and transmitting
l Auto-sensing 10/100Mbps media speed, full/half -duplex mode, and flow-control
capability
l Two switching mechanisms
- Supports ‘store and forward’ switching with filtering CRC-bad packets
- Supports ‘cut through’ switching subject to long packets of length over 64 bytes
l Packet buffering
- Glueless 32-bit interface to SSRAM as a packet buffer pool
- 64 packet buffers for 32Kx32 SSRAM, 149 packet buffers for 64Kx32 SSRAM
- 1536 bytes for each packet buffer
l Storing control data (forwarding table and packet link entries) in external SSRAM
- Buffer status is stored in the internal free-buffer bit map registers
- Shared forwarding table of 2K entries (or 4K slots) to support multiple (up to 4K)
Mac addresses per port
l Efficient address recognition, self learning, and auto-aging mechanism
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- Two-slot hashing algorithm to prevent hash collision
- Two optional hashing algorithms, CRC-map and direct-map
l Advanced congestion control mechanism
- IEEE 802.3X compliant flow control for full duplex ports
- Backpressure for half duplex ports
- Drop control for full duplex ports without flow control capability
- Incorporating with the output private buffering scheme to prevent HOL (head of line)
blocking
l Supports port mirroring (Sniffer feature)
l By-pass VLAN packets
l Support port-based trunking
- Support two individual trunk groups, each of 2 member ports
- Load balance according to DMAC address and source port number
l Support chip initialization through EEPROM or by strapping only
- Supports I2C EEPROM interface for customized configuration
- Supports LED serial-out in the strapping-only initialization mode
l 50MHz internal reference clock rate
l 83~100MHz SSRAM clock rate, typically 83MHz
l Single +3.3V supply, 0.3µm TSMC CMOS technology
l 128-pin PQFP package
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6 Page



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部品番号部品説明メーカ
VT6508

8 RMII PORTS OF 10/100BASE-T/TX ETHERNET SWITCH CONTROLLER

VIA
VIA


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