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PDF SI7216DN Data sheet ( Hoja de datos )
| Número de pieza | SI7216DN | |
| Descripción | Dual N-Channel 40-V (D-S) MOSFET | |
| Fabricantes | Vishay Siliconix | |
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Dual N-Channel 40-V (D-S) MOSFET
Si7216DN
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
0.032 at VGS = 10 V
40
0.039 at VGS = 4.5 V
ID (A)
6e
5e
Qg (Typ.)
5.5 nC
PowerPAK 1212-8
FEATURES
• Halogen-free According to IEC 61249-2-21
Available
• TrenchFET® Power MOSFET
• Low Thermal Resistance PowerPAK®
Package with Small Size and Low 1.07 mm
Profile
• 100 % Rg and UIS tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Primary Side Switch
• Synchronus Rectification
3.30 mm
D1
8 D1
7
D2
6 D2
5
S1
1
G1
2
3.30 mm
S2
3 G2
4
Bottom View
Ordering Information: Si7216DN-T1-E3 (Lead (Pb)-free)
Si7216DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
D1 D2
G1 G2
S1
N-Channel MOSFET
S2
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Limit
Unit
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Pulsed Drain Current
Continuous Source-Drain Diode Current
Avalanche Current
Single-Pulse Avalanche Energy
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)c, d
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
TC = 25 °C
TA = 25 °C
L = 0.1 mH
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
VDS
VGS
ID
IDM
IS
IAS
EAS
PD
TJ, Tstg
40
± 20
6e
5e
6.5a, b
5.2a, b
20
6e
2a, b
10
5
20.8
13.3
2.5a, b
1.6a, b
- 50 to 150
260
V
A
mJ
W
°C
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequade bottom side solder interconnection.
d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Package limited.
Document Number: 73771
www.vishay.com
S11-1142-Rev. C, 13-Jun-11
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
Si7216DN
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100 0.20
10
150 °C
1
0.16
0.12
0.1
0.01
25 C
0.001
0
0.2 0.4 0.6 0.8 1.0
VSD - Source-to-Drain Voltage (V)
1.2
Source-Drain Diode Forward Voltage
0.4
ID = 250 µA
0.2
0 ID = 5 mA
- 0.2
- 0.4
- 0.6
0.08
125 °C
0.04
25 °C
0.00
0 1 2 3 4 5 6 7 8 9 10
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
50
40
30
20
10
- 0.8
- 50 - 25
0 25 50 75 100 125 150
TJ - Temperature (°C)
Threshold Voltage
100
Limited by RDS(on)*
10
0
0.001
0.01
0.1 1
Time (s)
10
100 1000
Single Pulse Power, Junction-to-Ambient
1 ms
1
10 ms
100 ms
0.1 1 s
10 s
TA = 25 °C
Single Pulse
0.01
0.1
1
DC
10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
Document Number: 73771
www.vishay.com
S11-1142-Rev. C, 13-Jun-11
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
AN822
Vishay Siliconix
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package
Configuration
SO-8
Single Dual
TSSOP-8
Single Dual
TSOP-8
Single Dual
Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90
PPAK 1212
Single Dual
2.4 5.5
PPAK SO-8
Single Dual
1.8 5.5
PowerPAK 1212
49.8 °C
Standard SO-8
85 °C
Standard TSSOP-8
149 °C
TSOP-6
125 °C
2.4 °C/W
PC Board at 45 °C
20 °C/W
52 °C/W
Figure 4. Temperature of Devices on a PC Board
40 °C/W
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the tempera-
ture of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4).
Suppose each device is dissipating 2 W. Using the junc-
tion-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the Pow-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
nal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many appli-
cations. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No signif-
icant effect was observed.
Document Number 71681
03-Mar-06
www.vishay.com
3
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