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PDF SI570 Data sheet ( Hoja de datos )
| Número de pieza | SI570 | |
| Descripción | (SI570 / SI571) ANY-RATE I2C PROGRAMMABLE XO/VCXO | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si570/Si571
1 0 M H Z TO 1 . 4 G H Z I 2C P ROGRAMMABLE X O / V C X O
Features
Any programmable output
Internal fixed crystal frequency
frequencies from 10 to 945 MHz and ensures high reliability and low
select frequencies to 1.4 GHz
aging
I2C serial interface
Available LVPECL, CMOS,
3rd generation DSPLL® with superior LVDS, and CML outputs
jitter performance
3x better frequency stability than
SAW-based oscillators
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
ATE
High performance
instrumentation
Low-jitter clock generation
Optical modules
Clock and data recovery
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL®
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-
programmable to any output frequency from 10 to 945 MHz and select frequencies
to 1400 MHz with <1 ppb resolution. The device is programmed via an I2C serial
interface. Unlike traditional XO/VCXOs where a different crystal is required for
each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL
clock synthesis IC to provide any-frequency operation. This IC-based approach
allows the crystal resonator to provide exceptional frequency stability and
reliability. In addition, DSPLL clock synthesis provides superior supply noise
rejection, simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems.
Functional Block Diagram
VDD CLK- CLK+
OE
SDA
Fixed
Frequency
XO
10-1400 MHz
DSPLLClock
Synthesis
Si571 only
ADC
VC
GND
SCL
Si5602
Ordering Information:
See page 32.
Pin Assignments:
See page 31.
(Top View)
SDA
NC 1
7
6
VDD
OE 2
5 CLK–
GND 3
4 CLK+
8
SCL
Si570
VC 1
SDA
7
6 VDD
OE 2
5 CLK–
GND 3
4
8
SCL
Si571
CLK+
Rev. 1.5 4/14
Copyright © 2014 by Silicon Laboratories
Si570/Si571
1 page  
Si570/Si571
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition Min Typ Max Unit
3.3 V option
2.97
3.3 3.63
Supply Voltage1
VDD 2.5 V option
1.8 V option
2.25
1.71
2.5
2.75
V
1.8 1.89
Supply Current
Output enabled
LVPECL
— 120 130
CML
IDD LVDS
— 108 117
— 99 108 mA
CMOS
— 90 98
Output Enable (OE)2,
Serial Data (SDA),
Serial Clock (SCL)
TriState mode
VIH
VIL
—
0.75 x VDD
—
60
—
—
75
—
0.5 V
Operating Temperature Range
TA
–40 — 85 ºC
Notes:
1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 32 for further details.
2. OE pin includes a 17 k pullup resistor to VDD. See “7.Ordering Information”.
Table 2. VC Control Voltage Input (Si571)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
33
45
Control Voltage Tuning Slope1,2,3 KV VC 10 to 90% of VDD
—
90
135
— ppm/V
180
356
Control Voltage Linearity4
BSL –5 ±1 +5
LVC
Incremental
%
–10 ±5 +10
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
VC Input Impedance
Nominal Control Voltage5
ZVC
VCNOM
@ fO
500 —
— k
— VDD/2 —
V
Control Voltage Tuning Range
VC
0
VDD
V
Notes:
1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 32.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope is
determined with VC ranging from 10 to 90% of VDD.
5. Nominal output frequency set by VCNOM = 1/2 x VDD.
Rev. 1.5
5
5 Page 
Si570/Si571
Table 6. CLK± Output Phase Jitter (Si571) (Continued)
Parameter
Phase Jitter (RMS)1,2,3,5
for FOUT of 125 to
500 MHz
Symbol
Test Condition
J Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Min
—
—
Typ
0.37
0.33
Max Unit
ps
—
—
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.37
0.33
—
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.43
0.34
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.50
0.34
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.59
0.35
—
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
1.00
0.39
—
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Single ended mode: CMOS. Refer to the following application notes for further information:
“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”
“AN256: Integrated Phase Noise”
“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”
5. Max offset frequencies:
80 MHz for FOUT > 250 MHz
20 MHz for 50 MHz < FOUT <250 MHz
2 MHz for 10 MHz < FOUT <50 MHz.
Table 7. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min Typ
Max Unit
Period Jitter*
JPER
RMS
Peak-to-Peak
—2
— 14
—
ps
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to “AN279: Estimating Period Jitter
from Phase Noise” for further information.
Rev. 1.5
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI570.PDF ] | |
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