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V58C2256404SC の電気的特性と機能

V58C2256404SCのメーカーはProMOS Technologiesです、この部品の機能は「256 Mbit DDR SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 V58C2256404SC
部品説明 256 Mbit DDR SDRAM
メーカ ProMOS Technologies
ロゴ ProMOS Technologies ロゴ 




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V58C2256404SC Datasheet, V58C2256404SC PDF,ピン配置, 機能
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V58C2256(804/404/164)SC*I
256 Mbit DDR SDRAM, INDUSTRIAL TEMPERATURE
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
Clock Cycle Time (tCK2)
Clock Cycle Time (tCK2.5)
Clock Cycle Time (tCK3)
System Frequency (fCK max)
5B
DDR400
7.5 ns
5ns
5ns
200 MHz
5
DDR400
7.5 ns
6ns
5ns
200 MHz
6
DDR333
7.5 ns
6 ns
6 ns
166 MHz
7
DDR266
7.5ns
7ns
7 ns
143 MHz
Features
High speed data transfer rates with system frequency
up to 200 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 66-pin 400 mil TSOP or 60 Ball FBGA
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
Power Supply 2.6V ± 0.1V for DDR400
tRAS lockout supported
Concurrent auto precharge option is supported
Industrial Temperature (TA): -40C to +85C
*Note: (-5B) Supports PC3200 module with 2.5-3-3 timing
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-7) Supports PC2100 module with 2-2-2 timing
Description
The V58C2256(804/404/164)SC*I is a four bank DDR
DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x
4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). The
V58C2256(804/404/164)SC*I achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
JEDEC 66 TSOP II
60 FBGA
-40°C to +85°C
V58C2256(804/404/164)SC*I Rev.1.4 March 2007
CK Cycle Time (ns)
-5B -5
-6
•••
1
-7
Power
Std.
L
Temperature
Mark
I
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1 Page





V58C2256404SC pdf, ピン配列
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ProMOS TECHNOLOGIES
V58C2256(804/404/164)SC*I
60-Ball FBGA PIN OUT
(x4) 1
23
78
9 (x8) 1
23
78
9
VSSQ NC VSS A VDD NC VDDQ
NC VDDQ DQ3 B DQ0 VSSQ NC
NC VSSQ NC C
NC VDDQ NC
NC VDDQ DQ2 D DQ1 VSSQ NC
NC VSSQ DQS
VREF VSS DM
E
F
NC VDDQ NC
NC VDD NC
CK CK G
A12 CKE H
WE
RAS
CAS
CS
A11 A9 J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS M VDD A3
X4 Device Ball Pattern
VSSQ DQ7 VSS A VDD DQ0 VDDQ
NC VDDQ DQ6 B DQ1 VSSQ NC
NC VSSQ DQ5 C DQ2 VDDQ NC
NC VDDQ DQ4 D DQ3 VSSQ NC
NC VSSQ DQS
VREF VSS DM
E
F
NC VDDQ NC
NC VDD NC
CK CK G
A12 CKE H
WE
RAS
CAS
CS
A11 A9 J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS M VDD A3
X8 Device Ball Pattern
(x16) 1
23
78
9
VSSQ DQ15 VSS A VDD DQ0 VDDQ
DQ14 VDDQ DQ13 B DQ2 VSSQ DQ1
DQ12 VSSQ DQ11 C DQ4 VDDQ DQ3
DQ10 VDDQ DQ9 D DQ6 VSSQ DQ5
DQ8 VSSQ UDQS
VREF VSS UDM
E
F
LDQS VDDQ DQ7
LDM VDD NC
CK CK G WE CAS
A12 CKE H RAS CS
A11 A9 J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS M VDD A3
X16 Device Ball Pattern
PIN A1 INDEX
123
A
B
789
C
D
E
F
G
H
J
K
L
M
TOP VIEW
(See the ball through the package)
V58C2256(804/404/164)SC*I Rev. 1.4 March 2007
3
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3Pages


V58C2256404SC 電子部品, 半導体
www.DataSheet.co.kr
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SC*I
Block Diagram
32M x 8
Column Addresses
A0 - A9, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
8192 x 512
x 16 bit
Row decoder
Memory array
Bank 1
8192 x 512
x 16 bit
Row decoder
Memory array
Bank 2
8192 x 512
x 16bit
Row decoder
Memory array
Bank 3
8192 x 512
x 16bit
CK, CK
DQS
Input buffer Output buffer
DLL
Strobe
Gen.
DQ0-DQ7
Data Strobe
Control logic & timing generator
V58C2256(804/404/164)SC*I Rev. 1.4 March 2007
6
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6 Page



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部品番号部品説明メーカ
V58C2256404S

HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp
V58C2256404SC

256 Mbit DDR SDRAM

ProMOS Technologies
ProMOS Technologies


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