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L74VHC1GT04のメーカーはLRCです、この部品の機能は「Inverting Buffer / CMOS Logic Level Shifter」です。 |
部品番号 | L74VHC1GT04 |
| |
部品説明 | Inverting Buffer / CMOS Logic Level Shifter | ||
メーカ | LRC | ||
ロゴ | |||
このページの下部にプレビューとL74VHC1GT04ダウンロード(pdfファイル)リンクがあります。 Total 6 pages
LESHAN RADIO COMPANY, LTD.
Inverting Buffer / CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
L74VHC1GT04
The L74VHC1GT04 is a single gate inverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power supply.
The L74VHC1GT04 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the L74VHC1GT04 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• High Speed: t PD = 3.8 ns (Typ) at V CC = 5 V
• Low Power Dissipation: I CC = 2 mA (Max) at T A = 25°C
• TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V
• CMOS–Compatible Outputs: V OH > 0.8 V CC ;
V OL < 0.1 V CC @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic
Families
• Chip Complexity: FETs = 105; Equivalent Gates = 26
PIN ASSIGNMENT
5
4
1
2
3
SC–70/SC–88A/SOT–353
DF SUFFIX
5
4
1
2
3
SOT–23/TSOP–5/SC–59
DT SUFFIX
MARKING DIAGRAMS
VKd
Pin 1
d = Date Code
VKd
Pin 1
d = Date Code
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
PIN ASSIGNMENT
1 NC
2 IN A
3 GND
4 OUT Y
5 V CC
www.DataSheet4U.com
FUNCTION TABLE
Inputs
A
L
H
Output
Y
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 5 of this data sheet.
1/6
1 Page LESHAN RADIO COMPANY, LTD.
DC ELECTRICAL CHARACTERISTICS
Symbol
V IH
Parameter
Minimum High–Level
Input Voltage
Test Conditions
V IL Maximum Low–Level
Input Voltage
V OH
V OL
I IN
I CC
I CCT
I OPD
Minimum High–Level
Output Voltage
V IN = V IH or V IL
Maximum Low–Level
Output Voltage
V IN = V IH or V IL
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
Quiescent Supply
Current
Output Leakage
Current
V IN = V IH or V IL
I OH = – 50 µA
V IN = V IH or V IL
I OH = –4 mA
I OH = –8 mA
V IN = V IH or V IL
I OL = 50 µA
V IN = V IH or V IL
I OL = 4 mA
I OL = 8 mA
V IN = 5.5 V or GND
V IN = V CC or GND
Input: V IN = 3.4 V
V OUT = 5.5 V
L74VHC1GT04
V CC T A = 25°C T A < 85°C –55°C<TA<125°C
(V) Min Typ Max Min Max Min Max Unit
V
3.0 1.4
1.4 1.4
4.5 2.0
2.0 2.0
5.5 2.0
2.0 2.0
V
3.0 0.53 0.53 0.53
4.5 0.8 0.8 0.8
5.5 0.8 0.8 0.8
V
3.0 2.9 3.0
2.9 2.9
4.5 4.4 4.5
4.4 4.4
3.0 2.58
4.5 3.94
2.48 2.34
3.80 3.66
3.0 0.0 0.1 0.1 0.1
4.5 0.0 0.1 0.1 0.1
V
3.0
4.5
0 to5.5
0.36
0.36
±0.1
0.44
0.44
±1.0
0.52
0.52
±1.0
µA
5.5 2.0 20 40 µA
5.5 1.35 1.50 1.65 mA
0.0 0.5 5.0 10 µA
AC ELECTRICAL CHARACTERISTICS C load = 50 pF, Input t r = t f = 3.0 ns
T A = 25°C
T A < 85°C –55°C<TA<125°C
Symbol Parameter
Test Conditions
Min Typ Max Min Max Min Max Unit
t PLH , Maximum
V CC = 3.3± 0.3 V C L = 15 pF
5.0 10.0
11.0 13.0 ns
t PHL Propagation Delay,
C L = 50 pF
6.2 13.5
15.0 17.5
Input A or B to Y
V CC = 5.0± 0.5 V C L = 15 pF
3.8 6.7
7.5 8.5
C L = 50 pF
4.2 7.7
8.5 9.5
C IN Maximum Input
5 10
10 10 pF
Capacitance
Typical @ 25°C, V CC = 5.0 V
C PD Power Dissipation Capacitance (Note 6)
10
pF
6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without
.load. Average operating current can be obtained by the equation: I CC(OPR) = C PD • V CC • f in + I CC C PD is used to determine the no–
load dynamic power consumption; P D = C
PD
•
V
2
CC
•
f in + I CC •
V
CC .
3/6
3Pages LESHAN RADIO COMPANY, LTD.
D
54
S 1 23
L
G
A
B
0.05 (0.002)
H
C
L74VHC1GT04
PACKAGE DIMENSIONS
SOT23−5/TSOP−5/SC59−5
DT SUFFIX
J
KM
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
MILLIMETERS
DIM MIN MAX
A 2.90 3.10
B 1.30 1.70
C 0.90 1.10
D 0.25 0.50
G 0.85 1.05
H 0.013 0.100
J 0.10 0.26
K 0.20 0.60
L 1.25 1.55
M 0 _ 10_
S 2.50 3.00
INCHES
MIN MAX
0.1142 0.1220
0.0512 0.0669
0.0354 0.0433
0.0098 0.0197
0.0335 0.0413
0.0005 0.0040
0.0040 0.0102
0.0079 0.0236
0.0493 0.0610
0_ 10_
0.0985 0.1181
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
1.0
0.039
2.4
0.094
0.7
0.028
ǒ ǓSCALE 10:1
mm
inches
6/6
6 Page | |||
ページ | 合計 : 6 ページ | ||
|
PDF ダウンロード | [ L74VHC1GT04 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
L74VHC1GT00 | 2-Input NAND Gate / CMOS Logic Level Shifter | LRC |
L74VHC1GT01 | 2-Input NAND Gate with Open Drain Output | LRC |
L74VHC1GT02 | 2-Input NOR Gate / CMOS Logic Level Shifter | LRC |
L74VHC1GT03 | 2-Input NOR Gate with Open Drain Output | LRC |