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Número de pieza | R5H30211 | |
Descripción | Microcomputer | |
Fabricantes | Renesas | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de R5H30211 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
No Preview Available ! R5H30211
Renesas Microcomputer
REJ03B0259-0110
Rev.1.10
Jun. 05, 2009
Overview
This LSI is a single-chip microcontroller unit (MCU) built around the H8/300H CPU. Four I/O ports, ROM, RAM,
EEPROM, a random number generator (RNG), a watchdog timer (WDT), a firewall management unit (FMU), interval
timers (TMR1/TMR2), I2C bus interface (IIC2), synchronous serial communication unit (SSU), and a coprocessor are
included.
Operating at a maximum 10-MHz internal clock rate, the H8/300H CPU rapidly executes bit manipulation instructions,
arithmetic and logic instructions, and data transfer instructions.
The on-chip coprocessor executes modular multiplications (such as ABR-1 modN + kN), which are used to calculate
modular exponentiation XY modN, and DES calculation processing at a high speed.
Table 1 lists the features of this LSI.
Table 1 Features
CPU
Item
I/O ports
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Specification
H8/300H CPU
Upper compatible with the H8/300 CPU in the object level
Sixteen 16-bit registers (Sixteen 8-bit registers + eight 16-bit registers or Eight 32-bit registers)
• High-speed operation
Maximum clock rate: internal clock 10 MHz
Add/subtract: 0.20 µs (10 MHz)
Multiply/divide: 1.40 µs (10 MHz)
• Streamlined, concise instruction set
16-bit variable instruction length: 2 to 10 bytes
arithmetic and logic operations between registers
MOV instruction for data transfer between registers and memory
• Maximum 16-Mbyte address space
• Instruction set features
8-, 16-, or 32-bit transfer or arithmetic instructions
Unsigned or signed multiply instruction (8 bits × 8 bits and 16 bits × 16 bits)
Unsigned or signed divide instruction (16 bits ÷ 8 bits and 32 bits ÷ 16 bits)
Bit-accumulator instructions
• Register-indirect specification of bit positions
EEPROM write instruction (EEPMOV.B instruction)
High-speed block transfer instruction (EEPMOV.W instruction)
• Four general-purpose input/output ports (Also used for interrupts)
Note: When writing to the DDR7 to DDR4 bits, use the MOV instruction instead of the bit
manipulation instruction.
REJ03B0259-0110 Rev.1.10 Jun. 05, 2009
Page 1 of 17
1 page R5H30211
Pin Assignment
Figure 2 shows the pin arrangement of this LSI.
NC
P4/SCS/IRQ
CLK
RES
VCC
20 19 18 17 16
1 15
2 14
3
(Top view)
13
4 12
5 11
6 7 8 9 10
NC
P3/SSCK/IRQ
P1/SSI/SDA/IRQ
P2/SSO/SCL/IRQ
VSS
Figure 2 Pin Assignment
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REJ03B0259-0110 Rev.1.10 Jun. 05, 2009
Page 5 of 17
5 Page R5H30211
CLK
φ
Double of oscillator clock
φ
Same as on-chip oscillator
clock
φ
Half of on-chip oscillator clock
tscyc
tscyc
tscyc
Figure 4.3 System Clock Timing (External clock)
I/O port
(input)
VIH
VIL
tf
VIH
VIL
tr
Figure 5 I/O Port Input Waveform
VCC
CLK
1.8 V
VIH
VIL
0.8V
RES
VIL
ton tRWL1
VIL
VIL
tRWL2
VIL
tRWL2
toff
Note: At power-on and after power-off, Vcc, CLK, and RES pins should be
driven low (GND level).
Figure 6 Power ON/OFF and RES Input Timing
CLK
(in sleep mode 2)
Sleep mode 2
CLK
(in sleep mode 1)
Sleep mode 1
VIH
IRQ
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tCLKH
Program
execution state
Power-down state
VIL VIL
tCLKS tIRQW
Exception handling state
SLEEP instruction
IRQ
Figure 7 Interrupt Timing in Sleep Mode 1 and Sleep Mode 2
REJ03B0259-0110 Rev.1.10 Jun. 05, 2009
Page 11 of 17
11 Page |
Páginas | Total 19 Páginas | |
PDF Descargar | [ Datasheet R5H30211.PDF ] |
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