PDF STE2004 Data sheet ( Hoja de datos )

Número de pieza	STE2004
Descripción	102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER
Fabricantes	STMicroelectronics
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No Preview Available ! STE2004www.DataSheet4U.com 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER 1 FEATURES ■ 102 x 65 bits Display Data RAM ■ Programmable MUX rate ■ Programmable Frame Rate ■ X,Y Programmable Carriage Return ■ Dual Partial Display Mode ■ Row by Row Scrolling ■ N-Line Inversion ■ Automatic data RAM Blanking procedure ■ Selectable Input Interface: • I2C Bus Fast and Hs-mode (read and write) • 68000 & 8080 Parallel Interfaces (read and write) • 3-lines and 4-lines SPI Interface (read and write) • 3-lines 9 bit Serial Interface (read and write) ■ Fully Integrated Oscillator requires no external components ■ CMOS Compatible Inputs ■ Fully Integrated Configurable LCD bias voltage generator with: • Selectable multiplication factor (up to 5X) • Effective sensing for High Precision Output • Eight selectable temperature compensation coefficients ■ Designed for chip-on-glass (COG) applications. ■ Low Power Consumption, suitable for battery operated systems ■ Logic Supply Voltage range from 1.7 to 3.6V ■ High Voltage Generator Supply Voltage range from 1.75 to 4.5V ■ Display Supply Voltage range from 4.5 to 14.5V ■ Backward Compatibility with STE2001/2 2 DESCRIPTION The STE2004 is a low power CMOS LCD control- ler driver. Designed to drive a 65 rows by 102 col- umns graphic display, it provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption. STE2004 features six standard interfaces (3-lines Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel, 8080 parallel & I2C) for ease of interfacing with the host micro-controller Table 1. Order Codes Part Numbers Type STE2004DIE1 STE2004DIE2 Bumped Wafers Bumped Dice on Waffle Pack Figure 1. Block Diagram CO to C101 R0 to R64 OSC_IN OSC_OUT FR_IN FR_OUT VSENSE SLAVE VLCD VLCDSENSE RES VSSAUX VDD1,2 VSS SEL1,2 OSC MASTER SLAVE SYNC BIAS VOLTAGE GENERATOR TIMING GENERATOR CLOCK COLUMN DRIVERS DATA LATCHES ROW DRIVERS SHIFT REGISTER HIGH VOLTAGE GENERATOR RESET DATA REGISTER 65 x 102 RAM SCROLL LOGIC TEST INSTRUCTION REGISTER DISPLAY CONTROL LOGIC I2C BUS 9 Bit SERIAL 3 & 4 Line SPI Parallel 8080 Parallel 68K TEST_MODE TEST_VREF ICON_MODE EXT SEL 0 SEL 1 SEL 2 July 2004 SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD D/C to DB7 CS LR0047 Rev. 4 1/66 1 page Figure 3. Improved ALTH & PLESKO Driving Method STE2004 www.DataSheet4U.com VLCD V2 V3 ROW 0 R0 (t) V4 V5 VSS VLCD V2 V3 ROW 1 R1 (t) V4 V5 VSS VLCD V2 V3 COL 0 C0 (t) V4 V5 VSS VLCD V2 V3 COL 1 C1 (t) V4 V5 VSS VLCD - VSS V3 - VSS VLCD - V2 Vstate1(t) 0V V3 - VSS VLCD - VSS V3 - VSS VLCD - V2 Vstate2(t) 0V V3 - VSS 0 1 2 3 4 5 6 7 8 9 ....... FRAME n ∆V1(t) = C1(t) - R0(t) ∆V2(t) = C1(t) - R1(t) ∆V1(t) ∆V2(t) ..... 64 0 1 2 3 4 5 6 7 8 9 ....... FRAME n + 1 V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD V4 - V5 0V VSS - V5 ..... 64 V4 - VLCD VSS - VLCD D00IN1154 5/66 5 Page STE2004 Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM wNwowrm.DaaltaFSohremeta4tU.(cMoXm=0)1 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 0123 98 99 100 101 LR0049 Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)1 0123 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 98 99 100 101 LR0050 Figure 10. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)1 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 101 100 99 98 3210 LR0051 Figure 11. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)1 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 101 100 99 98 1. X Carriage=101; Y-Carriage = 8 3210 LR0052 11/66 11 Page

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