|
|
PDF GS8642Z36 Data sheet ( Hoja de datos )
| Número de pieza | GS8642Z36 | |
| Descripción | 72Mb Pipelined and Flow Through Synchronous NBT SRAM | |
| Fabricantes | GSI Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de GS8642Z36 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Product Preview
GS8642Z18(B)/GS8642Zw3w6w(.BDa)/tGaSShe8e6t44U2.cZo7m2(C)
119- & 209-Bump BGA
Commercial Temp
Industrial Temp
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–167 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119- or 209-bump BGA package
• Pb-Free 119- and 209-bump BGA packages available
Functional Description
The GS8642Z18/36/72 is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8642Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8642Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-300 -250 -200 -167 Unit
tKQ(x18/x36)
tKQ(x72)
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
2.3 2.5 3.0 3.5 ns
3.0 3.0 3.0 3.5 ns
3.3 4.0 5.0 6.0 ns
400 340 290 260 mA
480 410 350 305 mA
590 520 435 380 mA
5.5 6.5 7.5 8.0 ns
5.5 6.5 7.5 8.0 ns
285 245 220 210 mA
330 280 250 240 mA
425 370 315 300 mA
Rev: 1.02 5/2005
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
1 page  
Product Preview
GS8642Z18(B)/GS8642Zw3w6w(.BDa)/tGaSShe8e6t44U2.cZo7m2(C)
GS8642Z36B Pad Out–119-Bump BGA—Top View
1234567
A VDDQ A A A A A VDDQ A
B NC E2 A ADV A E3 NC B
C NC A
A VDD A
A NC C
D
DQC DQPC
VSS
ZQ
VSS DQPB DQB
D
E
DQC DQC
VSS
E1
VSS DQB DQB
E
F
VDDQ
DQC
VSS
G
VSS
DQB
VDDQ
F
G
DQC DQC
BC
A
BB DQB DQB
G
H
DQC DQC
VSS
W
VSS DQB DQB
H
J
VDDQ
VDD
NC
VDD
NC
VDD VDDQ
J
K
DQD DQD
VSS
CK
VSS DQA DQA
K
L
DQD DQD
BD
NC
BA DQA DQA
L
M
VDDQ
DQD
VSS
CKE
VSS
DQA
VDDQ
M
N
DQD DQD
VSS
A1
VSS DQA DQA
N
P
DQD DQPD
VSS
A0
VSS DQPA DQA
P
R NC A LBO VDD FT A NC R
T NC A A A A A ZZ T
U
VDDQ
TMS
TDI
TCK
TDO
NC VDDQ
U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.02 5/2005
5/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
5 Page 
Product Preview
GS8642Z18(B)/GS8642Zw3w6w(.BDa)/tGaSShe8e6t44U2.cZo7m2(C)
Pipeline Mode Data I/O State Diagram
Intermediate
BW
High Z
(Data In)
R
D
Intermediate
Intermediate
W
Intermediate
RB
Data Out
(Q Valid)
D
Intermediate
WR
High Z
B
D
Intermediate
Key
Input Command Code
ƒ Transition
Transition
Current State (n) Intermediate State (N+1) Next State (n+2)
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
n
n+1 n+2 n+3
Command
ƒƒƒƒ
Current State
Intermediate
State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.02 5/2005
11/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GS8642Z36.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| GS8642Z36 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM | GSI Technology |
| GS8642Z36B | 72Mb Pipelined and Flow Through Synchronous NBT SRAM | GSI Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |