DataSheet.jp

GS815036AB-333 の電気的特性と機能

GS815036AB-333のメーカーはGSI Technologyです、この部品の機能は「1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS815036AB-333
部品説明 1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




このページの下部にプレビューとGS815036AB-333ダウンロード(pdfファイル)リンクがあります。
Total 25 pages

No Preview Available !

GS815036AB-333 Datasheet, GS815036AB-333 PDF,ピン配置, 機能
Product Preview
GS815018/3w6wAwB.D-3at5a7Sh/3ee3t34U/3.c0o0m/250
119-Bump BGA
Commercial Temp
Industrial Temp
1M x 18, 512K x 36
18Mb Register-Register Late Write SRAM
250 MHz–357 MHz
2.5 V VDD
HSTL I/O
Features
• Register-Register Late Write mode, Pipelined Read mode
• 2.5 V +200/–200 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• ZQ controlled programmable output drivers
• Dual Cycle Deselect
• Fully coherent read and write pipelines
• Byte write operation (9-bit bytes)
• Differential HSTL clock inputs, K and K
• Asynchronous output enable
• Sleep mode via ZZ
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• JEDEC-standard 119-bump BGA package
• Pb-Free 119-bump BGA package available
Family Overview
GS815018/36A are 18,874,368-bit (18Mb) high performance
SRAMs. This family of wide, low voltage HSTL I/O SRAMs
is designed to operate at the speeds needed to implement
economical high performance cache systems.
Functional Description
Because GS815018/36A are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
GS815018/36A support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
GS815018/36A are implemented with high performance
technology and are packaged in a 119-bump BGA.
Mode Control
There are two mode control select pins (M1 and M2), which
allow the user to set the correct read protocol for the design.
The GS815018/36A support single clock Pipeline mode, which
directly affects the two mode control select pins. In order for
the part to fuction correctly, and as specified, M1 must be tied
to VSS and M2 must be tied to VDD or VDDQ. This must be set
at power-up and should not be changed during operation.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Pipeline
Parameter Synopsis
-357 -333 -300 -250 Unit
Cycle
tKHQV
2.8 3.0 3.3 4.0 ns
1.4 1.5 1.6 2.0 ns
Curr (x18)
Curr (x36)
600 550 500 450 mA
650 600 550 500 mA
Rev: 1.05 10/2005
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

1 Page





GS815036AB-333 pdf, ピン配列
Product Preview
GS815018/3w6wAwB.D-3at5a7Sh/3ee3t34U/3.c0o0m/250
GS815018 Pinout—119-Bump BGA—Top View (Package B)
1234567
A
VDDQ
A
A NC A
A VDDQ
B
NC A
A NC A
A NC
C
NC A
A VDD A
A NC
D DQB NC VSS ZQ VSS DQA NC
E NC DQB VSS SS VSS NC DQA
F
VDDQ
NC
VSS
G
VSS
DQA
VDDQ
G NC DQB BB NC NC NC DQA
H DQB NC VSS NC VSS DQA NC
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K NC DQB VSS CK VSS NC DQA
L DQB NC NC CK BA DQA NC
M
VDDQ
DQB
VSS
SW
VSS
NC VDDQ
N DQB NC VSS A VSS DQA NC
P NC DQB VSS A VSS NC DQA
R NC A M1 VDD M2 A NC
T
NC A
A NC A
A ZZ
U
VDDQ
TMS
TDI
TCK TDO
NC
VDDQ
Rev: 1.05 10/2005
3/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology


3Pages


GS815036AB-333 電子部品, 半導体
Product Preview
GS815018/3w6wAwB.D-3at5a7Sh/3ee3t34U/3.c0o0m/250
Register-Register Late Write, Pipelined Read Truth Table
CK ZZ SS SW Bx G
Current Operation
DQ
(tn)
DQ
(tn+1)
X 1 X XX X
Sleep (Power Down) mode
Hi-Z
Hi-Z
0 1 XX X
Deselect
*** Hi-Z
0 0 1X 1
Read
Hi-Z/ Hi-Z
0 0 1X 0
Read
*** Q(tn)
0 0 00X
Write All Bytes
*** D(tn)
0 0 0XX
Write Bytes with Bx = 0
***
D(tn)
0 0 01X
Write (Abort)
*** Hi-Z
Notes:
1. If one or more Bx = 0, then B = “T” else B = “F”.
2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”.
3. “***” indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation.
4. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
5. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
6. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
Rev: 1.05 10/2005
6/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

6 Page



ページ 合計 : 25 ページ
 
PDF
ダウンロード
[ GS815036AB-333 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
GS815036AB-333

1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM

GSI Technology
GSI Technology


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap