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PDF LC7872E Data sheet ( Hoja de datos )
| Número de pieza | LC7872E | |
| Descripción | CD Graphics Decoder | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : EN4868A
CMOS LSI
LC7872E
CD Graphics Decoder
Overview
The LC7872E is a CMOS LSI that integrates in a single
chip the signal processing functions required for compact
disk graphics (CD-G) decoding. The LC7872E accepts the
subcode R to W signals output by a CD-DSP chip such as
the Sanyo LC786X series, LC7862XE series or
LC7863XE series and performs de-interleaving, error
detection and correction, graphics instruction processing
and image processing.
Functions
• Built-in RGB encoder allows a CD-G decoder to be
implemented in just two chips: the LC7872E and an
external 64-kword × 4-bit DRAM
• Interpolation and protection for the CD subcode
synchronization signals as well as de-interleaving, error
detection and correction for the R to W signals.
• Two crystal oscillator systems, one for NTSC and one
for PAL are provided and can be switched easily using
the control pin provided. The standard clock and all
required internal timings can be generated by
connecting a 14.31818 MHz crystal for NTSC and/or a
17.734476 MHz crystal for PAL.
• The LC7872E performs CD graphics instruction
processing and drawing processing and controls the
image display.
• Composition video 8-bit D/A converter output provided
• Superimposition support
• Microprocessor interface provided to support set
upgrades.
• Define transparency support
• Color bar output function
Features
• A CD-G decoder can be implemented with just two
chips: a controller is not required.
• Silicon gate CMOS structure for low power operation
• Single 5 V power supply
• 64-pin QFP (QIP) package
Package Dimensions
unit: mm
3159-QFP64E
[LC7872E]
SANYO: QFP64E
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
O3097HA (OT)/20695TH (OT) No. 4868-1/17
1 page  
LC7872E
Figure 1 Microcontroller Interface Timing
A0 to A7
DB0 to DB3
Figure 2 DRAM Read Cycle
No. 4868-5/17
5 Page 
LC7872E
Pin Applications
1. Crystal Clock Oscillator; XIN1, XOUT1, XIN2, XOUT2, N/P1, N/P2, FSC, CSYNC, LINE and VSYNC
The LC7872E provides two crystal oscillator systems as follows.
Pins XIN1 and XOUT1 are for use with a 14.31818 MHz crystal oscillator (NTSC)
Pins XIN2 and XOUT2 are for use with a 17.734476 MHz crystal oscillator (PAL)
Crystals can be connected to either crystal system 1 or 2 according to the application, or both systems can be used
under the control of pins N/P1 and N/P2 to implement an application that supports both video standards. The N/P1
pin switches the LC7872E RGB encoder block between NTSC and PAL and the N/P2 pin switches the decoder block
between NTSC and PAL. The FSC pin outputs a clock that is the crystal oscillator frequency divided by four. The
CSYNC pin is the composite synchronization signal output and VSYNC is the vertical synchronization signal output.
The LINE pin switches the number of lines on a screen.
The table below lists the pin states in each mode.
XIN1, XOUT1
14.31818 MHz
*
14.30244 MHz
XIN2, XOUT2
*
17.734476 MHz
*
N/P1 N/P2
High High
Television system
NTSC/M
Low Low
PAL/GBIDH
Low High
PAL/M
FSC
3.579545 MHz
4.433619 MHz
3.575611 MHz
LINE
H
L
H
L
H
L
CSYNC
16.71511323 ms
16.65155767 ms
19.96788628 ms
20.09588555 ms
16.73350841 ms
16.6698829 ms
2. Subcode Interface; S1, S2, SBSY, SFSY, PW, SBCK and MUTE
The LC7872E supports three interface modes under the control of pins S1 and S2. When the MUTE pin is set high,
SBSY and PW input is disabled and SBCK output stops.
S1
S2
Mode
Low
Low
LC7861N/67 interface
High
Low
LC7860K/63 interface
High
High
LC7868/69/681 interface
The SBCK delivery condition is that SFSY be confirmed to be low about 2.2 µs after the SFSY falling edge in
LC7860K/63 interface mode. In the other interface modes, the condition is that SFSY be confirmed to be high and
SBSY be confirmed to be low about 2.2 µs after the SFSY rising edge.
• LC7860 interface (Pin names in parentheses are LC7860 pins.)
Note: 1. PWSY will be high during the S0 and S1 periods.
2. The SBSY pin must be held low.
No. 4868-11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet LC7872E.PDF ] | |
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