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PDF LC78625E Data sheet ( Hoja de datos )
| Número de pieza | LC78625E | |
| Descripción | Compact Disc Player DSP | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : EN5502
CMOS LSI
LC78625E
Compact Disc Player DSP
Overview
The LC78625E is a CMOS LSI that implements the signal
processing and servo control required by compact disc
players, laser discs, CD-V, CD-I and related products. The
LC78625E provides several types of signal processing,
including demodulation of the optical pickup EFM signal,
de-interleaving, error detection and correction, and digital
filters that can help reduce the cost of CD player units. It
also processes a rich set of servo system commands sent
from the control microprocessor. It also incorporates an
EFM-PLL circuit and a one-bit D/A converter.
This LSI is an improved version of the LC78620E. In
addition to supporting low-voltage operation, on/off
control of the de-emphasis function and use of the
bilingual function have been enabled in certain additional
modes.
Functions
• The LC78625E takes an HF signal as input, digitizes
(slices) that signal at a precise level, converts that signal
to an EFM signal, and generates a PLL clock with an
average frequency of 4.3218 MHz by comparing the
phases of that signal and an internal VCO.
• A precise reference clock and the necessary internal
timings are generated using an external 16.9344 MHz
crystal oscillator.
• Disc motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection, and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microprocessor
• Subcode Q signal output (LSB first) to a microprocessor
over the serial interface after performing a CRC error
check
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disc rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
• The LC78625E sets the C2 flags based on the C1 flags
and a C2 check, and then performs signal interpolation
or muting depending on the C2 flags. The interpolation
circuit uses a quadruple interpolation scheme. The
output value converges to the muting level when four or
more consecutive C2 flags occur.
Package Dimensions
unit: mm
3174-QFP80E
[LC78625E]
SANYO: QFP80E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT) No. 5502-1/35
1 page  
LC78625E
One-Bit D/A Converter Analog Characteristics at Ta = 25°C, VDD = LVDD = RVDD = 5 V, VSS = LVSS = RVSS = 0 V
Parameter
Total harmonic distortion
Dynamic range
Signal-to-noise ratio
Crosstalk
Symbol
Conditions
LCHP, RCHP, LCHN, RCHN;
THD + N 1 kHz: 0 dB data input, using the 20 kHz
low-pass filter (AD725D built in)
LCHP, RCHP, LCHN, RCHN;
DR 1 kHz: –60 dB data input, using the 20 kHz
low-pass filter and the A filter (AD725D built in)
LCHP, RCHP, LCHN, RCHN;
S/N 1 kHz: 0 dB data input, using the 20 kHz
low-pass filter and the A filter (AD725D built in)
LCHP, RCHP, LCHN, RCHN;
CT 1 kHz: 0 dB data input, using the 20 kHz
low-pass filter (AD725D built in)
min
84
98
96
Ratings
typ
0.008
88
100
98
Note: Measured with the normal-speed playback mode digital attenuator in the Sanyo one-bit D/A converter block reference circuit.
Unit
max
0.0010
%
dB
dB
dB
Figure 1 Command Input
Figure 2 Subcode Q Output
Figure 3 Subcode Output
No. 5502-5/35
5 Page 
LC78625E
3. VCO monitor; Pin 21: PCK
PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is the VCO frequency divided by two.
4. Synchronization detection monitor; Pin 22: FSEQ
Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal
read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is
thus a synchronization detection monitor. (It is held high for a single frame.)
5. Servo command function; Pin 64: RWC, pin 66: COIN, pin 67: CQCK
Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with
the CQCK clock. Note that commands are executed on the falling edge of RWC.
Focus start
Track jump
Muting control
Disc motor control
Miscellaneous control
One byte commands
Track check
Two-byte command (RWC set twice)
Digital attenuator
General-purpose port I/O data setup
• One-byte commands
Two-byte commands (RWC set once)
• Two-byte commands (RWC set twice)
• Two-byte commands (RWC set once)
No. 5502-11/35
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LC78625E.PDF ] | |
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