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LC78624E の電気的特性と機能

LC78624EのメーカーはSanyo Semicon Deviceです、この部品の機能は「Compact Disc Player DSP」です。


製品の詳細 ( Datasheet PDF )

部品番号 LC78624E
部品説明 Compact Disc Player DSP
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 




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LC78624E Datasheet, LC78624E PDF,ピン配置, 機能
Ordering number : EN5811
CMOS LSI
LC78624E
Compact Disc Player DSP
Overview
The LC78624E is a CMOS LSI that implements the signal
processing and servo control required by compact disc
players. Including an EFM-PLL and text decoder, the
LC78624E strictly limits functionality to basic signal
processing and servo system operation to achieve the best
cost-performance balance for low-end players. As basic
functions, the LC78624E provides demodulation of the
EFM signal from the optical pickup, de-interleaving, error
detection and correction, and processes servo commands
sent from the control microcontroller.
Functions
• Input signal processing: The LC78624E takes an HF
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
an internal VCO.
• Precise reference clock and necessary internal timing
generation using an external 16.9344 MHz crystal
oscillator
• Disk motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microcontroller
• Subcode Q signal output to a microcontroller over the
serial I/O interface after performing a CRC error check
(LSB first)
• Serial output to a microcontroller via the text decoder of
the song titles and other text data stored in the Subcode
R through W channels of the read-in area
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disk rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
• The LC78624E sets the C2 flags based on the C1 flags
and a C2 check, and then performs signal interpolation
or muting depending on the C2 flags. The interpolation
circuit uses a dual-interpolation scheme. The previous
value is held if the C2 flags indicate errors two or more
times consecutively.
• Support for command input from a microcontroller:
commands include track jump, focus start, disk motor
start/stop, muting on/off and track count (8 bit serial
input)
• Built-in digital output circuits.
• Arbitrary track counting to support high-speed data
access
• Zero cross muting
• Supports the implementation of a double-speed dubbing
function.
• Support for bilingual applications.
• General-purpose I/O ports: 5 pins
Features
• 64 pin QFP
• 5 V single-voltage power supply
Package Dimensions
unit: mm
3159-QFP64E
[LC78624E]
SANYO: QIP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
20698RM (OT) No. 5811-1/27

1 Page





LC78624E pdf, ピン配列
LC78624E
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN
VOUT
Pd max
Topr
Tstg
Conditions
Allowable Operating Ranges at Ta = 25°C, VSS = 0 V
Parameter
Supply voltage
Input high level voltage
Input low level voltage
Data setup time
Data hold time
High level clock pulse width
Low level clock pulse width
Data read access time
Command transfer time
Subcode Q read enable time
Subcode read cycle time
Subcode read enable time
Port input data setup time
Port input data hold time
Port input clock setup time
Port output data delay time
Input level
Operating frequency range
Crystal oscillator frequency
Text readout time
DQSY pulse width
SCLK “low” level pulse width
SCLK “high” level pulse width
SCLK delay time
Text data delay time
Reset time
Symbol
Conditions
VDD (1)
VDD (2)
VIH (1)
VIH (2)
VIL (1)
VIL (2)
tSU
tHD
tWH
tWL
tRAC
tRWC
tSQE
tSC
tSE
tCSU
tCHD
tRCQ
tCDD
VIN (1)
VIN (2)
fop
fX
tCW
tW
tWTL
tWTH
tD1
tD2
tD3
tRES
VDD, XVDD, VVDD:
During normal-speed playback
VDD, XVDD, VVDD:
During double-speed playback
DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,
TAI, TEST1 to TEST6, CS, CONT1 to CONT5, SCLK
EFMIN
DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,
TAI, TEST1 to TEST6, CS, CONT1 to CONT5, SCLK
EFMIN
COIN, RWC: Figure 1
COIN, RWC: Figure 1
SBCK, CQCK: Figures 1, 2 and 3
SBCK, CQCK: Figures 1, 2 and 3
SQOUT, PW: Figures 2 and 3
RWC: Figure 1
WRQ: Figure 2, with no RWC signal
SFSY: Figure 3
SFSY: Figure 3
CONT1 to CONT5, RWC: Figure 4
CONT1 to CONT5, RWC: Figure 4
RWC, CQCK: Figure 4
CONT1 to CONT5, RWC: Figure 5
EFMIN: Slice level control
XIN: Capacitor-coupled input
EFMIN
XIN, XOUT
DQSY : Figure 6.
DQSY : Figure 6.
SCLK : Figure 6.
SCLK : Figure 6.
SCLK : Figure 6.
SRDT : Figure 6.
SRDT : Figure 6.
RES
Ratings
VSS – 0.3 to VSS + 7.0
VSS – 0.3 to VDD + 0.3
VSS – 0.3 to VDD + 0.3
300
–20 to +75
–40 to +125
Unit
V
V
V
mW
°C
°C
min
3.0
Ratings
typ
max
5.5
Unit
V
3.0
0.7 VDD
0.6 VDD
0
0
400
400
400
400
0
1000
400
400
400
100
1.0
1.0
1.5
60
100
100
100
400
11.2
136
16.9344
3.3
136
5.5
VDD
VDD
0.3 VDD
0.4 VDD
400
1200
10
3.7
150
50
50
V
V
V
V
V
ns
ns
ns
ns
ns
ns
ms
µs
ns
ns
ns
ns
ns
Vp-p
Vp-p
MHz
MHz
ms
µs
ns
ns
ns
ns
ns
ns
No. 5811-3/27


3Pages


LC78624E 電子部品, 半導体
LC78624E
Figure 4 General-Purpose Port Input Timing
A09897
Figure 5 General-Purpose Port Output Timing
A09898
Figure 6 Text Data Output Timing
A09899
No. 5811-6/27

6 Page



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部品番号部品説明メーカ
LC78624E

Compact Disc Player DSP

Sanyo Semicon Device
Sanyo Semicon Device


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