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PDF V386 Data sheet ( Hoja de datos )

Número de pieza V386
Descripción 8-BIT LVDS RECEIVER FOR VIDEO
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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V386
8-BIT LVDS RECEIVER FOR VIDEO
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General Description
Features
The V386 is an ideal LVDS receiver that converts 4-pair
LVDS data streams into parallel 28 bits of CMOS/TTL
data with bandwidth up to 2.38 Gbps throughput or
297.5 Mbytes per second.
This chip is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL
interfaces through very low-swing LVDS signals.
ICS manufactures a large variety of video application
devices. Consult ICS for all of your video application
requirements.
Pin and function compatible with the National
DS90CF386, THine THC63LVDF84, TI
SN65LVDS94
Converts 4-pair LVDS data streams into parallel 28
bits of CMOS/TTL data
Fully spread spectrum compatible
Wide clock frequency range from 20 MHz to 85 MHz
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Pin Assignments
RxOUT22
RxOUT23
RxOUT24
GND
RxOUT25
RxOUT26
RxOUT27
LVDS_GND
RxIN0-
RxIN0+
RxIN1-
RxIN1+
LVDS_VCC
LVDS_GND
RxIN2-
RxIN2+
RxCLKIN-
RxCLKIN+
RxIN3-
RxIN3+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWRDWN
RxCLKOUT
RxOUT0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VCC
55 RxOUT21
54 RxOUT20
53 RxOUT19
52 GND
51 RxOUT18
50 RxOUT17
49 RxOUT16
48 VCC
47 RxOUT15
46 RxOUT14
45 RxOUT13
44 GND
43 RxOUT12
42 RxOUT11
41 RxOUT10
40 VCC
39 RxOUT9
38 RxOUT8
37 RxOUT7
36 GND
35 RxOUT6
34 RxOUT5
33 RxOUT4
32 RxOUT3
31 VCC
30 RxOUT2
29 RxOUT1
Low-power CMOS design
Falling edge clock triggered outputs
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Packaged in a 56-pin TSSOP (Pb free available)
Block Diagram
RxIN0+
RxIN0-
RxIN1+
RxIN1-
RxIN2+
RxIN2-
RxIN3+
RxIN3-
RxCLKIN+
RxCLKIN-
PWRDWN
LVDS to TTL
De-serializer
PLL
8 RED
8 GREEN
8 BLUE
HSYNC
VSYNC
DATA ENABLE
CONTROL
RxCLKOUT
V386
56-pin TSSOP
V386
V386 Datasheet
1
5/25/05
Revision 2.0
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

1 page




V386 pdf
V386
8-BIT LVDS RECEIVER FOR VIDEO
Parameter
Symbol
Conditions
0V
Output Short Circuit Current
LVDS Receiver DC Specifications
IOS VOUT = 0V
Differential Input High Threshold
Differential Input Low Threshold
Input Current
Receiver Supply Current
VTH VCM = +1.2 V
VTL
IIN VIN = +2.4 V, VCC = 3.6 V
VIN = 0V, VCC = 3.6 V
Receiver Supply Current (worst case) ICCRW CL = 8 pF, f = 65 MHz, worst
case pattern
CL = 8 pF, f = 85 MHz, worst
case pattern
Receiver Supply Current (16
Grayscale)
ICCRG CL= 8 pF, f = 65 MHz, 16
Grayscale pattern
CL= 8 pF, f = 85 MHz, 16
Grayscale pattern
Receiver Supply Current (Power
Down)
ICCRZ
Power_Down = Low,
Receiver outputs stay low
during Power-down mode
Receiver Switching Characteristics
CMOS/TTL Low-to-High Transition
Time
CLHT 20% to 80% VCC, CL= 8 pF
CMOS/TTL High-to-Low Transition
Time
CHLT 80% to 20% VCC, CL= 8 pF
CLKOUT period
RCOP
CLKOUT High Time
RCOH f = 85 MHz
CLKOUT Low Time
RCOL f = 85 MHz
Data Setup to CLKOUT
RSRC f = 85 MHz
Data Hold to CLKOUT
RHRC f = 85 MHz
RCK+/- to CLKOUT Delay
RCCD 25°C / 3.3 V
Receiver PLL Setup Time
RPLLS
Receiver Power Down Delay
RPDD
Receiver Input Strobe Position for
Bit0
RSPos0 f = 85 MHz, T = 11.76 ns
Receiver Input Strobe Position for
Bit1
RSPos1 f = 85 MHz, T = 11.76 ns
Receiver Input Strobe Position for
Bit2
RSPos2 f = 85 MHz, T = 11.76 ns
Receiver Input Strobe Position for
Bit3
RSPos3 f = 85 MHz, T = 11.76 ns
Receiver Input Strobe Position for
Bit4
RSPos4 f = 85 MHz, T = 11.76 ns
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Min.
Typ.
Max.
±10
-60
Units
mA
-100
+100
±10
±15
mV
mV
µA
µA
220 mA
240 mA
125 mA
140 mA
140 400 µA
11.76
4.5
4
2.0
3.5
8
2
1.8
T
5
5
14
0.49 0.84
2.17 2.52
3.85 4.2
5.53 5.88
7.21 7.56
3.5
3.5
50
7
6.5
20
10
1
1.19
2.87
4.55
6.23
7.91
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
ns
ns
ns
ns
ns
V386 Datasheet
5
5/25/05
Revision 2.0
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

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