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GS8160V36CT の電気的特性と機能

GS8160V36CTのメーカーはGSI Technologyです、この部品の機能は「1M x 18 and 512K x 36 18Mb Sync Burst SRAMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS8160V36CT
部品説明 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS8160V36CT Datasheet, GS8160V36CT PDF,ピン配置, 機能
Preliminary
GS8160Vw1w8w/3.D6aCtaTSh-e3e3t43U/3.c0om0/250
100-Pin TQFP
Commercial Temp
Industrial Temp
1M x 18 and 512K x 36
18Mb Sync Burst SRAMs
333 MHz250 MHz
1.8 V VDD
1.8 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS8160V18/36CT is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160V18/36CT operates on a 1.8 V power supply. All
input are 1.8 V compatible. Separate output power (VDDQ)
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-333 -300 -250 Unit
tKQ
tCycle
2.5 2.5 2.5 ns
3.0 3.3 4.0 ns
Curr (x18)
Curr (x32/x36)
375 335 280 mA
435 390 330 mA
tKQ
tCycle
4.5 5.0 5.5 ns
4.5 5.0 5.5 ns
Curr (x18)
Curr (x32/x36)
280 230 210 mA
335 270 240 mA
Rev: 1.00 9/2004
1/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

1 Page





GS8160V36CT pdf, ピン配列
GS8160V36C 100-Pin TQFP Pinout
Preliminary
GS8160Vw1w8w/3.D6aCtaTSh-e3e3t43U/3.c0om0/250
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
512K x 36
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
Rev: 1.00 9/2004
3/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology


3Pages


GS8160V36CT 電子部品, 半導体
Preliminary
GS8160Vw1w8w/3.D6aCtaTSh-e3e3t43U/3.c0o0m/250
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO L
H
Linear Burst
Interleaved Burst
Output Register Control
L
FT H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ H
Active
Standby, IDD = ISB
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00 9/2004
6/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

6 Page



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部品番号部品説明メーカ
GS8160V36CT

1M x 18 and 512K x 36 18Mb Sync Burst SRAMs

GSI Technology
GSI Technology


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