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PDF LC75863W Data sheet ( Hoja de datos )

Número de pieza LC75863W
Descripción 1/3 Duty LCD Display Drivers with Key Input Function
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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No Preview Available ! LC75863W Hoja de datos, Descripción, Manual

Ordering number : ENN7135
CMOS IC
LC75863E, 75863W
1/3 Duty LCD Display Drivers with Key Input Function
Overview
The LC75863E and LC75863W are 1/3 duty LCD display
drivers that can directly drive up to 75 segments and can
control up to four general-purpose output ports. These
products also incorporate a key scan circuit that accepts
input from up to 30 keys to reduce printed circuit board
wiring.
Features
• Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
• 1/3duty - 1/2bias and 1/3duty - 1/3bias drive schemes
can be controlled from serial data (up to 75 segments).
• Sleep mode and all segments off functions that are
controlled from serial data.
• Segment output port/general-purpose output port
function switching that is controlled from serial data.
• Serial data I/O supports CCB format communication
with the system controller.
• Direct display of display data without the use of a
decoder provides high generality.
• Independent VLCD for the LCD driver block (VLCD can
be set to in the range VDD-0.5 to 6.0 volts.)
• Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.
• RC oscillator circuit.
Package Dimensions
unit: mm
3156-QIP48E
1.5
36
37
[LC75863E]
17.2
14.0
1.0 0.35
1.6
1.5
25
24
0.15
48
1
13
12
0.1
2.7
0.8 15.6
SANYO: QIP48E
unit: mm
3163A-SQFP48
[LC75863W]
9.0
7.0
0.75 0.5 0.18
36
37
25
0.75 0.15
24
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
48
1
13
12
0.5 0.5
SANYO: SQFP48
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D2001TN (OT) No. 7135-1/24

1 page




LC75863W pdf
Block Diagram
LC75863E, 75863W
VLCD
VLCD1
VLCD2
VSS
TEST
OSC
DO
DI
CL
CE
VDD
COMMON
DRIVER
CLOCK
GENERATOR
CCB
INTERFACE
VDET
SEGMENT DRIVER & LATCH
SHIFT REGISTER
CONTROL
REGISTER
KEY BUFFER
KEY SCAN
No. 7135-5/24

5 Page





LC75863W arduino
LC75863E, 75863W
Output Data
1. KD1 to KD30 : Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
KS1/S24
KS2/S25
KS3
KS4
KS5
KS6
KI1
KD1
KD6
KD11
KD16
KD21
KD26
KI2
KD2
KD7
KD12
KD17
KD22
KD27
KI3
KD3
KD8
KD13
KD18
KD23
KD28
KI4
KD4
KD9
KD14
KD19
KD24
KD29
KI5
KD5
KD10
KD15
KD20
KD25
KD30
When the KS1/S24 and KS2/S25 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2. SA : Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data
is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data
bits, even in sleep mode. (See the control data description for details.)
No. 7135-11/24

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