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PDF LC75010W Data sheet ( Hoja de datos )
| Número de pieza | LC75010W | |
| Descripción | LC75010W Car Audio DSP | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : ENN7349
CMOS IC
LC75010W
LC75010W Car Audio DSP
Overview
The LC75010W is a car audio DSP IC that integrates the
signal processing required by car audio systems, A/D and
D/A converters, volume control, and other functions on a
single chip. It can implement a car audio system with a
minimal number of external components.
Features
• Hardware Functions
— Analog source selector (BTL:1ch, OTL:3 ch)
— 20 bits A/D (2ch)
— 24 bits DSP (core, program memory, data memory)
— SIO (CCB I/F) (CCB is LSB first input.)
— 24 bits D/A (4ch)
— EVR (4ch)
• Software Functions* (See Note.)
— Bass/Mid/Treb
— Bal/Fad
— Fixed equalizer (Front/Rear/separately controlled)
— Loudness control
— Hybrid volume
— Anti-hard clip
— Dedekind (Speaton**)
Note *: Software specifications can be modified in
response to user requests.
• DSP Functions (24 fixed-point DSP)
— Program ROM — 8k words
— Data RAM — 896 words
• Supply Voltage and Package Specifications
— DSP core, A/D converter (digital block), D/A
converter (digital block): 3.3 V
— A/D converter (analog block), D/A converter
(analog block), volume control, crystal oscillator:
5V
— Package: 100-pin SQFP (14×14 mm)
Package Dimensions
unit: mm
3181C-SQFP100
[LC75010W]
16.0
14.0
75 51
76 50
100
1 0.5
(1.0)
26
0.2 25
0.145
SANYO: SQFP100
• CCB is a registered trademark of Sanyo Electric Co., Ltd.
• CCB is Sanyo's original bus format. All bus addresses are managed by Sanyo for this format.
Note **: Speaton is a registered trademark of Dedekind R&D. Users who want to develop, manufacture,
or sell electronic equipment that uses Dedekind functions must enter a separate contract with
Dedekind R&D for the use of those functions.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N2103TN (OT) No. 7349-1/12
1 page  
Pin Functions
Pin No.
97
94
77
80
89
85
92
82
93
81
Pin name
AINRP1
AINRN1
AINLP1
AINLN1
AINRP2
AINLP2
AINRP3
AINLP3
AINRP4
AINLP4
34 PWDB
35 RSTB
40 INTB
10 TEST0
11 TEST1
12 TEST2
13 TEST3
14 TEST4
17 TEST5
18 TEST6
19 TEST7
20 TEST8
21 TEST9
22 TEST10
41 TEST11
44 TEST12
45 TEST13
46 TEST14
49 XIN
50 XOUT
27 VCO
28 PDO
36 CE
37 CL
38 DI
39 DO
33 BUSY
74 VFLO
73 VFLI
71 VFRO
70 VFRI
58 VRLO
59 VRLI
55 VRRO
56 VRRI
LC75010W
Input/Output (I/O)
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
O
I
I
I
O
O
O
I
O
I
O
I
O
I
Function
Analog BTL input (Rch +)
Analog BTL input (Rch -)
Analog BTL input (Lch +)
Analog BTL input (Lch -)
Analog OTL input1 (Rch +)
Analog OTL input1 (Lch +)
Analog OTL input2 (Rch +)
Analog OTL input2 (Lch +)
Analog OTL input3 (Rch +)
Analog OTL input3 (Lch +)
Standby mode (active low)
Setting the PWDB pin to the low level sets the LC75010W to standby mode (also know as "power
down mode").
In standby mode, the DSP system clock and the crystal oscillator are stopped and the whole
LC75010W goes to the stopped state. This pin must be held at the high level during normal
operation.
Reset (active low)
A reset is normally applied at power on, after recovering from a temporary power outage, and after
returning from standby mode ("power down mode").
Interrupt (active low) (Software clip input (0/1))
Provides feedback control to the DSP to prevent clipping when an overflow occurs in the amplifier
output.
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Crystal input (384 fs = 16.9344 MHz) (fs = 44.1 kHz)
Crystal output
VCO control
Charge pump output
CCB enable
CCB clock
Data in
Data out
CCB ready monitor
Outputs the state of the DSP CCB receive buffer.
A low-level output from the BUSY pin indicates that the buffer is empty.
A high-level output indicates that command data is present in the receive buffer.
Volume front Lch output
Volume front Lch input
Volume front Rch output
Volume front Rch input
Volume rear Lch output
Volume rear Lch input
Volume rear Rch output
Volume rear Rch input
Continued on next page.
No. N7349-5/12
5 Page 
Peripheral Circuit Example
LC75010W
No. N7349-11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LC75010W.PDF ] | |
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