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LC74798M の電気的特性と機能

LC74798MのメーカーはSanyo Semicon Deviceです、この部品の機能は「On-Screen Display Controller IC」です。


製品の詳細 ( Datasheet PDF )

部品番号 LC74798M
部品説明 On-Screen Display Controller IC
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 




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LC74798M Datasheet, LC74798M PDF,ピン配置, 機能
Ordering number : EN5833
CMOS IC
LC74798, 74798M
On-Screen Display Controller IC
Overview
The LC74798 and LC74798M are on-screen display
controller CMOS ICs that display characters and patterns
on the TV screen under microprocessor control. These ICs
include a built-in PDC/VPS/UDT interface circuit.
Features
• Display format: 24 characters by 12 rows (Up to 288
characters)
• Character format: 12 (horizontal) × 18 (vertical) dots
• Character sizes: Three sizes each in the horizontal and
vertical directions
• Characters in font: 128
• Initial display positions: 64 horizontal positions and
64 vertical positions
• Blinking: Specifiable in character units
• Blinking types: Two periods supported: 1.0 second and
0.5 second
• Blanking: Over the whole font (12 × 18 dots)
• Background color
— 8 colors (internal synchronization mode): 4fSC
— 6 colors (internal synchronization mode): 2fSC
— Blue background only: NTSC
• Line background color
— Three lines can be set up.
— 8 line background colors (in internal synchronization
mode): 4fSC
— 6 line background colors (in internal synchronization
mode): 2fSC
• External control input: 8-bit serial input format
• On-chip sync separator and AFC circuits
• On-chip PDC/VPS/UDT interface circuit
• Video outputs: PAL and NTSC format composite video
outputs
• Package: DIP30SD (400 mil)
MFP30S (375 mil)
Package Dimensions
unit: mm
3193-DIP30SD
[LC74798]
unit: mm
3216-MFP30S
[LC74798M]
SANYO: DIP30SD
SANYO: MFP30S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51898RM (OT) No. 5833-1/32

1 Page





LC74798M pdf, ピン配列
LC74798, 74798M
Pin Descriptions
Pin No.
1
2
3
Pin name
VSS1
XtalIN
XtalOUT
(MUTE)
Ground
Function
Crystal oscillator
(MUTE input)
Notes
Ground connection (digital system ground)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an
external clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to
function as the MUTE input pin. When this pin is set low, the video output is held at the
pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.)
CTRL1 Crystal oscillator input switching
4
(CHABLK) (CHABLK output)
5
CS2
Enable input 2
Switches the mode between external clock input and crystal oscillator operation. A low
level selects crystal oscillator operation and a high level selects external clock input. As a
mask option, the CTRL1 input pin can be set to function as the CHABLK (character ·
frame) output. This is a 3-value output.
Enable input for the PDC/VPS data output. Data output is enabled when this input is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
6 SCLK2 Clock input 2
Clock input for the PDC/VPS data output.
A pull-up resistor is built in and the input has hysteresis characteristics.
7 DOUT Data output
PDC/VPS data output.
(This can be either an n-channel open-drain output or a CMOS output.)
Outputs the state of the external synchronizing signal presence/absence judgment.
8
SYNCJDG
External synchronizing signal judgment Outputs a high level when synchronizing signals are present.
output
Outputs the crystal oscillator clock when CS1 and RST are low.
(This signal is not output on command resets.)
9
CS1
Enable input 1
Enable input for the OSD serial data input.
Serial data input is enabled when this pin is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
10 SCLK1 Clock input 1
Serial data input enable pin.
A pull-up resistor is built in and the input has hysteresis characteristics.
11 SIN1 Data input 1
Serial data input. A pull-up resistor is built in and the input has hysteresis characteristics.
12
VDD2
Power supply
13 CPOUT Charge pump output
Composite video signal level adjustment power supply (analog system power supply)
Charge pump output. Connect a low-pass filter to this pin.
14 VCOIN Oscillator control voltage input
VCO oscillator control voltage input. (For data slicing)
15
VSS3
Ground
16 VCOR Oscillator range adjustment
17 VCOIN2 Oscillator control voltage input 2
18
VDD3
Power supply (+5 V)
19 CVOUT Video signal output
20
VSS2
Ground
21
CVIN
Video signal input
22 CVCR Video signal input
23
VDD1
Power supply (+5 V)
24 SYNIN Sync separator circuit input
Ground (VCO ground)
VCO oscillator range adjustment resistor connection
VCO oscillator control voltage input. For character display.
Power supply (+5 V: VCO power supply)
Composite video signal output
Ground (analog system ground)
Composite video signal input
SECAM chrominance signal input
Power supply (+5 V: digital system power supply)
Video signal input to the internal sync separator circuit
25 SEPC Sync separator circuit adjustment Internal sync separator circuit adjustment
Internal sync separator circuit composite synchronizing signal output. Can be switched to
26 SEPOUT Composite synchronizing signal output function as a signal (high, low, or ST. pulse) output by the MOD0 setting when SEL0 is
high.
Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output
27
SEPIN Vertical synchronizing signal input
signal.
An integration circuit must be connected between this pin and the SEPOUT pin. This pin
must be tied to VDD1 if unused. This pin is valid when CTL3 is set high.
28 CDLR Background color phase adjustment Background color phase adjustment resistor connection
29
RST
Reset input
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
30
VDD1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
Note *: A capacitor of at least 2000 pF must be connected between the VDD1 power supply and VSS1.
No. 5833-3/32


3Pages


LC74798M 電子部品, 半導体
LC74798, 74798M
Figure 1 OSD Serial Data Input Timing
<Test Load>
Note: DOUT goes to the high-impedance state while CS2 is high.
Figure 2 PDC/VPS Serial Output Test Conditions (For the n-channel open-drain output circuit type.)
No. 5833-6/32

6 Page



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部品番号部品説明メーカ
LC74798

On-Screen Display Controller IC

Sanyo Semicon Device
Sanyo Semicon Device
LC74798M

On-Screen Display Controller IC

Sanyo Semicon Device
Sanyo Semicon Device


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