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LC74792 の電気的特性と機能

LC74792のメーカーはSanyo Semicon Deviceです、この部品の機能は「VPS / PDC Slicer IC」です。


製品の詳細 ( Datasheet PDF )

部品番号 LC74792
部品説明 VPS / PDC Slicer IC
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 




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LC74792 Datasheet, LC74792 PDF,ピン配置, 機能
Ordering number : EN*5965
CMOS IC
LC74792, 74792JM
VPS / PDC Slicer IC
Preliminary
Overview
The LC74792/JM is a CMOS IC that provides PDC, VPS,
and UDT data acquisition functions. The LC74792/JM
supports microprocessor control of its operating modes
and microprocessor read out of data acquired in any of its
operating modes.
Features
• VPS data acquisition (5 or 11 to 15 bytes)
VPS: Video Program System
• PDC (8/30/2) data acquisition (13 to 25 bytes)
PDC: Program Delivery Control
• UDT (8/30/1) data acquisition (13 to 25 bytes)
UDT: Unified Date and Time
• Header (X/00) data acquisition (14 to 45 bytes)
• Status display (8/30/1, 8/30/2) data acquisition (26 to
45 bytes)
• Automatic VPS/PDC discrimination mode
• Built-in AFC and sync separator circuits
• Synchronization discrimination circuit
Package Dimensions
unit: mm
3067-DIP24S
[LC74792]
24 13
1 12
21.2
0.81 1.78 0.48
0.95
unit: mm
3112-MFP24S
24
[LC74792JM]
13
SANYO: DIP24S
1 12
12.6 0.15
0.35 1.0 0.8
SANYO: MFP24S
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40299RM (OT) No. 5965-1/25

1 Page





LC74792 pdf, ピン配列
LC74792, 74792JM
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin
VSS1
XtalIN
XtalOUT
Ground
Function
Crystal oscillator connections
CTRL1 Crystal element switching
CS Enable input pin
SIO Data input/output pin
Digital system ground
Description
Connections for the crystal element and capacitors that form the crystal oscillator. Also
used for external clock input (fsc, 2fsc, or 4fsc).
Switches between external clock input mode and crystal oscillator mode. Set this pin low
for crystal oscillator, and high for external clock input.
Enable input pin (hysteresis input)
Data input/output pin (hysteresis input)
SCLK Clock input pin
Clock input pin (hysteresis input)
External synchronizing signal
SYNCJDG discrimination output
External synchronizing signal presence/absence discrimination status output.
A high level is output when synchronizing signals are present.
This pin outputs the crystal oscillator clock when the RST pin is low.
(This reset state output can be disabled with command input.)
Hout Horizontal synchronizing signal output Horizontal synchronizing signal output
VSS2
CPOUT
VCOIN
VCOR
Ground
Charge pump output
Oscillator control voltage input
Oscillator range adjustment
Ground. (VCO circuit ground)
Charge pump output. Connect a low-pass filter to this pin.
VCO oscillation control voltage input
VCO oscillation range adjustment resistor connection
DAV Data acquisition output
Outputs a low level when PDC/VPS data has been discriminated
VDD2
SYNIN
SEPC
Power supply (+5 V)
Sync separator circuit input
Slice level output
Power supply (+5 V) (VCO system power supply)
Internal sync separator circuit video signal input
Slice level verification
SEPOUT
SEPIN
Composite synchronizing signal output Internal sync separator circuit composite synchronizing signal output
Vertical synchronizing signal input
Inputs the vertical synchronizing signal by integrating the SEPOUT pin output signal.
Applications must connect the SEPOUT pin to this pin through an integration circuit. If
unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.)
Vout Vertical synchronizing signal output
Vertical synchronizing signal output
This pin outputs the VCO clock when the RST pin is low.
(This reset state output can be disabled with command input.)
CTRL2 SEPIN input control
Controls whether or not the VSYNC vertical synchronizing signal is input to the SEPIN
input.
When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.)
When high: The VSYNC signal is input.
CDLR Clock phase adjustment
Connection for the clock phase adjustment resistor
RST Reset input
System reset input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
VDD1 Power supply (+5 V)
Power supply. (+5 V: digital system power supply)
No. 5965-3/25


3Pages


LC74792 電子部品, 半導体
LC74792, 74792JM
Figure 1 Serial Data Input Timing
(Test load)
Figure 2 Serial Data Input Timing (in case of N-ch open-drain type)
No. 5965-6/25

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
LC74792

VPS / PDC Slicer IC

Sanyo Semicon Device
Sanyo Semicon Device
LC74792JM

VPS / PDC Slicer IC

Sanyo Semicon Device
Sanyo Semicon Device
LC74793

VPS / PDC Slicer IC

Sanyo Semicon Device
Sanyo Semicon Device
LC74793JM

VPS / PDC Slicer IC

Sanyo Semicon Device
Sanyo Semicon Device


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