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LC74725 の電気的特性と機能

LC74725のメーカーはSanyo Semicon Deviceです、この部品の機能は「On-Screen Display Controller LSI」です。


製品の詳細 ( Datasheet PDF )

部品番号 LC74725
部品説明 On-Screen Display Controller LSI
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 




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LC74725 Datasheet, LC74725 PDF,ピン配置, 機能
Ordering number : EN5213A
CMOS LSI
LC74725, 74725M
On-Screen Display Controller LSI
Overview
The LC74725 and LC74725M are built-in EDS on-screen
display controller CMOS LSI products that display
characters and patterns on a TV screen under
microprocessor control. The characters displayed have an
8 × 8 dot format, and a dot interpolation function is
provided. These LSIs can display ten lines of
24 characters each.
Features
• Display format: 24 characters by 10 lines (up to
240 characters)
• Character format: 8 (horizontal) × 8 (vertical) dots
(interpolation function provided)
• Character sizes: Two horizontal and two vertical sizes
• Characters in font: 64 characters
• Initial display positions: 64 horizontal positions and
64 vertical positions
• Blinking: Specifiable on a per-character basis
• Blinking types: Two periods, 1.0 second and 0.5 second
• Blue background screen display: Available in internal
synchronization mode
• External control input: 8-bit serial input format
• Built-in sync separator circuit
• EDS support
• Video outputs: Composite video signal output in either
NTSC or PAL-M
• Package: 24-pin plastic DIP (300 mil)
24-pin plastic MFP (375 mil)
Package Dimensions
unit: mm
3067-DIP24S
[LC7425]
3045B-MFP24
[LC7425M]
SANYO: DIP24S
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
41096HA (OT)/O3195HA (OT) No. 5213-1/16

1 Page





LC74725 pdf, ピン配列
LC74725, 74725M
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN max
VOUT max
Pd max
Topr
Tstg
Conditions
VDD1, VDD2
All input pins
LN21, CPDT, SEPOUT, SYNCJDG
Ta = 25°C
Ratings
VSS – 0.3 to VSS + 7.0
VSS – 0.3 to VDD + 0.3
VSS – 0.3 to VDD + 0.3
350
–30 to +70
–40 to +125
Unit
V
V
V
mW
°C
°C
Allowable Operating Ranges at Ta = –30 to +70°C
Parameter
Symbol
Conditions
Supply voltage
Input high level voltage
Input low level voltage
Pull-up resistance
VDD1
VDD2
VIH1
VIH2
VIL1
VIL2
RPU
VDD1
VDD2
RST, CS1, CS2, SIN, SCLK
CTRL1, SEPIN
RST, CS1, CS2, SIN, SCLK
CTRL1, SEPIN
Applies to RST, CS1, CS2, SIN, SCLK, and the pins
specified as options.
Composite video input voltage
Input voltage
Oscillator frequency
VIN1
VIN2
VIN3
fOSC1
fOSC1
fOSC1
fOSC1
fOSC2
CVIN: VDD1 = 5 V
SYNIN: VDD1 = 5 V
XtalIN (when external clock input is used),
fIN = 2fsc or 4fsc: VDD1 = 5 V
XtalIN, XtalOUT oscillator pins (2fsc: NTSC)
XtalIN, XtalOUT oscillator pins (4fsc: NTSC)
XtalIN, XtalOUT oscillator pins (2fsc: PAL-M)
XtalIN, XtalOUT oscillator pins (4fsc: PAL-M)
OSCIN, OSCOUT oscillator pins (LC oscillator)
Note: Extreme care must be used to prevent noise when the XtalIN pin is used in clock input mode.
min
4.5
4.5
0.8 VDD1
0.7 VDD1
VSS – 0.3
VSS – 0.3
25
1.5
0.1
5
typ
5.0
5.0
50
2.0
2.0
7.159
14.318
7.151
14.302
max
5.5
1.27 VDD1
VDD1 + 0.3
VDD1 + 0.3
0.2 VDD1
0.3 VDD1
Unit
V
V
V
V
V
V
90 k
Vp-p
2.5 Vp-p
5.0 Vp-p
MHz
MHz
MHz
MHz
12 MHz
Electrical Characteristics at Ta = –30 to +70°C, and unless otherwise specified, with VDD1 = 5 V
Parameter
Input off leakage current
Output off leakage current
Output high level voltage
Output low level voltage
Input current
Operating current drain
Sync level
Pedestal level
Color burst low level
Color burst high level
Background color low level
Background color high level
Symbol
Ileak1
Ileak2
VOH1
VOL1
IIH
IIL
IDD1
IDD2
VSN
VPD
VCBL
VCBH
VRSL
VRSH
Conditions
CVIN
CVOUT
LN21, SYNCJDG, CPDT, SEPOUT: VDD1 = 4.5 V,
IOH = –1.0 mA
LN21, SYNCJDG, CPDT, SEPOUT: VDD1 = 4.5 V,
IOL = 1.0 mA
RST, CS1, CS2, SIN, SCLK, CTRL1, SEPIN: VIN = VDD1
CTRL1, OSCIN: VIN = VSS1
VDD1: All outputs open, crystal: 7.159 MHz, LC: 8 MHz
VDD2: VDD2 = 5 V
When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V
When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V
min
3.5
–1
0.69
0.89
1.28
1.47
0.97
1.16
1.60
1.79
1.44
1.63
1.96
2.16
typ max Unit
1 µA
1 µA
V
1.0 V
0.81
1.01
1.40
1.59
1.09
1.28
1.72
1.91
1.56
1.75
2.08
2.28
1
30
20
0.98
1.13
1.52
1.71
1.21
1.40
1.84
2.03
1.68
1.87
2.20
2.40
µA
µA
mA
mA
V
V
V
V
V
V
V
V
V
V
V
V
Continued on next page.
No. 5213-3/16


3Pages


LC74725 電子部品, 半導体
LC74725, 74725M
Note: When closed caption character data is extracted in NTSC-TV mode (MOD0 is high), the control microprocessor can determine whether the current
field is an odd field or an even field by checking the signal level output by the SYNCJDG pin (when SEL0 is high) at the point it detects the rise of the
LN21 signal.
Figure 4 LC74725/M to Decoder LSI (or Microprocessor) Caption Data Transfer Technique 1
(This is the basic usage mode for these LSIs.)
Caption data transfer to the data output buffer is synchronized with the falling edge of the pulse output from LN21. Therefore, the following software
processing is required if the decoder LSI (or microprocessor) does not detect the fall of LN21.
When MOD0 is low, since the data is output to the data buffer once (during the even field) in a single frame, the decoder LSI (or microprocessor) must
perform the transfer control operation at least twice per frame (about 32 ms).
When the transfer control operation is performed twice in the same frame, the second CPDT 16 bits of output data are all zeros. Therefore, the
microprocessor must determine that the data for the next frame had not been transferred to the output buffer in this case.
Note: The LC74725 hardware will not transfer data to the output buffer while CS2 is low. Therefore the decoder LSI (or microprocessor) must restore CS2
from the low level to the high level after completing a data transfer control cycle.
This transfer technique (technique 2) cannot be used in NTSC-TV mode, i.e., when MOD0 is high.
Figure 5 LC74725/M to Decoder LSI (or Microprocessor) Caption Data Transfer Technique 2
(When a port to detect the fall of LN21 cannot be allocated in the decoder LSI (or Microprocessor).)
No. 5213-6/16

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
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On-screen Video Display Controller for NTSC or PAL-M

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On-screen Video Display Controllers for NTSC or PAL-M

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