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LC72722 の電気的特性と機能

LC72722のメーカーはSanyo Semicon Deviceです、この部品の機能は「Single-Chip RDS Signal-Processing System LSI」です。


製品の詳細 ( Datasheet PDF )

部品番号 LC72722
部品説明 Single-Chip RDS Signal-Processing System LSI
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 




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LC72722 Datasheet, LC72722 PDF,ピン配置, 機能
Ordering number : ENN6123A
CMOS IC
LC72722, 72722M, 72722PM
Single-Chip RDS
Signal-Processing System LSI
Overview
The LC72722 and LC72722M, LC72722PM are single-
chip system ICs that implement the signal processing
required by the European Broadcasting Union RDS (Radio
Data System) standard and by the US NRSC (National
Radio System Committee) RDBS (Radio Broadcast Data
System) standard. These ICs include band-pass filter,
demodulator, synchronization, and error correction circuits
as well as data buffer RAM on chip and perform effective
error correction using a soft-decision error correction
technique.
Functions
• Band-pass filter: Switched capacitor filter (SCF)
• Demodulator: RDS data clock regeneration and
demodulated data reliability information
• Synchronization: Block synchronization detection (with
variable backward and forward protection conditions)
• Error correction: Soft-decision/hard-decision error
correction
• Buffer RAM: Adequate for 24 blocks of data (about 500
ms) and flag memory
• Data I/O: CCB interface (power on reset)
Features
• Error correction capability improved by soft-decision
error correction
• The load on the control microprocessor can be reduced
by storing decoded data in the on-chip data buffer RAM.
• Two synchronization detection circuits provide
continuous and stable detection of the synchronization
timing.
• Data can be read out starting with the backward-
protection block data after a synchronization reset.
• Bit slip detection and correction
• Low spurious radiation
• Fully adjustment free
• Operating power-supply voltage: 4.5 to 5.5 V
• Operating temperature: –40 to +85°C
• Package: LC72722 : DIP24S
LC72722M : MFP24S
LC72722PM : MFP24
Package Dimensions
unit: mm
3067A-DIP24S
[LC72722]
21.0
24 13
1
0.9
12
(0.71) 1.78 0.48
0.95
SANYO: DIP24S
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51202AS (OT)/83199TH (OT) No. 6123-1/15

1 Page





LC72722 pdf, ピン配列
Pin Functions
Pin No.
Pin name
1 VREF
LC72722, 72722M, 72722PM
Function
Reference voltage output (Vdda/2)
I/O
Output
2
MPXIN
Baseband (multiplexed) signal input
Input
Pin circuit
Vdda
Vssa
Vdda
A12365
Vssa A12366
5
FLOUT
Subcarrier output (filter output)
6 CIN Subcarrier input (comparator input)
3
Vdda
Analog system power supply (+5 V)
4
Vssa
Analog system ground
12
XOUT
Crystal oscillator output (4.332/8.664 MHz)
Output
+
Vdda
A12367
Input
Output
Vssa
XIN
VREF
Vddd
A12368
13 XIN Crystal oscillator input (external reference signal input)
XOUT
Vssd
A12369
7
T1
Test input (This pin must always be connected to ground.)
Input
Test input (standby control)
8 T2 0: Normal operation, 1: Standby state (crystal oscillator stopped)
9
T3 (RDCL)
Test I/O (RDS clock output)
10
T4 (RDDA)
Test I/O (RDS data output)
11
T5 (RSFT)
Test I/O (soft-decision control data output)
Test I/O (error status output, regenerated carrier output,
16 T6 (ERROR/57K/TP/BE1) TP output, error block count output)
Test I/O (Error correction status output, SK detection output,
17 T7 (CORREC/ARI-ID/TA/BE0) TA output, error block count output)
18
SYNC
Block synchronization detection output
I/O*
19
RDS-ID
RDS detection output
20 DO Data output
Output
21 CL Clock input Serial data interface (CCB)
22 DI Data input
23 CE Chip enable
24
SYR
Synchronization and RAM address reset (active high)
14
Vddd
Digital system power supply (+5 V)
15
Vssd
Digital system ground
Input
Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications.
S
Vssd
A12370
Vssd
A12371
Vssd
A12372
S
Vssd
A12373
No. 5602-3/15


3Pages


LC72722 電子部品, 半導体
LC72722, 72722M, 72722PM
2. Offset word information flag (3 bits): B0 to B2
BBB
210
000
001
010
011
100
101
110
111
Offset word
A
B
C
C’
D
E
Unused
Unused
3. Consecutive RAM readout possible flag (1 bit): RE
RE RAM data information
1 The next data to be read out is in RAM.
0 This data item is the last item in RAM, and the next data is not present.
4. RAM data remaining flag (2 bits): RF0, RF1
RF1 RF0
00
01
10
11
Remaining data in RAM (number of blocks)
1 to 7
8 to 15
16 to 23
24
Caution: This value is only meaningful when RE is 1. When RE is 0, there is no data in RAM, even if RF is 00.
If a synchronization reset was applied using SYR, then the backward protection block data that was written to memory is also counted in this
value.
5. ARI (SK) detection flag (1 bit): ARI
ARI SK signal
1 Detected
0 Not detected
6. Synchronization established flag (1 bit): SYC
SYC Synchronization detection
1 Synchronized
0 Not synchronized
Caution: This flag indicates the synchronization state of the circuit at the point where the data block being output was received.
On the other hand, the SYNC pin (pin 18) output indicates the current synchronization state of the circuit.
7. Error information flags (3 bits): E0 to E2
EEE
210
Number of
bits corrected
000
0 (no errors)
001
1
010
2
011
3
100
4
101
5
1 1 0 Correction not possible
111
Unused
Caution: If the number of errors exceeds the value of the EC0 to EC2 setting (see the section on the CCB input format), the error information flags will be
set to the “Correction not possible” value.
When the error flags E0 to E2 are 011 (indicating that correction is not possible) the data must be handled as invalid data.
8. RDS data (16 bits): D0 to D15
This data is output with the MSB first and the LSB last.
Caution: When error correction was not possible, the input data is output without change.
No. 5602-6/15

6 Page



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