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PDF LC72720M Data sheet ( Hoja de datos )
| Número de pieza | LC72720M | |
| Descripción | Single-Chip RDS Signal-Processing System LSI | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : EN *5602
Preliminary
CMOS LSI
LC72720, 72720M
Single-Chip RDS
Signal-Processing System LSI
Overview
The LC72720 and LC72720M are single-chip system LSIs
that implement the signal processing required by the
European Broadcasting Union RDS (Radio Data System)
standard and by the US NRSC (National Radio System
Committee) RDBS (Radio Broadcast Data System)
standard. These LSIs include band-pass filter,
demodulator, synchronization, and error correction circuits
as well as data buffer RAM on chip and perform effective
error correction using a soft-decision error correction
technique.
Functions
• Band-pass filter: Switched capacitor filter (SCF)
• Demodulator: RDS data clock regeneration and
demodulated data reliability information
• Synchronization: Block synchronization detection (with
variable backward and forward protection conditions)
• Error correction: Soft-decision/hard-decision error
correction
• Buffer RAM: Adequate for 24 blocks of data (about 500
ms) and flag memory
• Data I/O: CCB interface (power on reset)
Package Dimensions
unit: mm
3067-DIP24S
[LC72720]
unit: mm
3045B-MFP24
[LC72720M]
SANYO: DIP24S
Features
• Error correction capability improved by soft-decision
error correction
• The load on the control microprocessor can be reduced
by storing decoded data in the on-chip data buffer RAM.
• Two synchronization detection circuits provide
continuous and stable detection of the synchronization
timing.
• Data can be read out starting with the backward-
protection block data after a synchronization reset.
• Fully adjustment free
• Operating power-supply voltage: 4.5 to 5.5 V
• Operating temperature: –40 to +85°C
• Package: DIP24S, MFP24
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
N2897HA (OT) No. 5602-1/14
1 page  
LC72720, 72720M
Continued from preceding page.
Parameter
Reference voltage output
Hysteresis
Output low-level voltage
Input high-level current
Input low-level current
Output off leakage current
Current drain
Symbol
Conditions
Vref
VHIS
VOL1
VOL2
IIH1
IIH2
IIL1
IIL2
IOFF
Idd
VREF : Vdda = 5 V
CL, DI, CE, SYR, T1, T2
DO, T3, T4, T5, T6, T7 : I = 2 mA
SYNC, RDS-ID : I = 8 mA
CL, DI, CE, SYR, T1, T2 : VI = 6.5 V
XIN : VI = Vddd
CL, DI, CE, SYR, T1, T2 : VI = 0 V
XIN : VI = 0 V
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 :
VO = 6.5 V
Vddd + Vdda
Ratings
min typ
2.5
0.1 Vddd
2.0
2.0
12
max
0.4
0.4
5.0
11
5.0
11
5.0
Unit
V
V
V
V
µA
µA
µA
µA
µA
mA
CCB Output Data Format
• Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.
• Any number of 32-bit output data blocks can be output consecutively.
• When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data
consecutively.
• If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted.
However, if only the last bit remains to be read, it will not be possible to reread that whole block.
• The check bits (10 bits) are not output.
CCB address 6C
Output data/first bit
1. Offset word detection flag (1 bit): OWD
OWD
1
0
Offset word detection
Detected
Not detected (protection function operating)
2. Offset word information flag (3 bits): B0 to B2
BBB
210
000
001
010
011
100
101
110
111
Offset word
A
B
C
C’
D
E
Unused
Unused
Last bit
(8) RDS data
(7) Error information flags
(6) Synchronization established flag
(5) ARI (SK) detection flag
(4) RAM data remaining flag
(3) Consecutive RAM read out possible flag
(2) Offset word information flag
(1) Offset word detection flag
Fixed pattern (1010)
No. 5602-5/14
5 Page 
LC72720, 72720M
Serial Data Input and Output Methods
Data is input and output using the CCB (computer control bus), which is the Sanyo audio LSI serial bus format. This LSI
adopts an 8-bit address CCB format.
(LSB)
Address
(MSB)
I/O mode
B0 B1 B2 B3 A0 A1 A2 A3
Comment
· Control data input mode, also referred to as “serial data input” mode.
1 IN1 (6A) 0 1 0 1 0 1 1 0 · This is a 16-bit data input mode.
· Control data input mode, also referred to as “serial data input” mode.
2 IN2 (6B) 1 1 0 1 0 1 1 0 · This is a 16-bit data input mode.
· Data output mode, also referred to as “serial data output” mode.
3 OUT (6C) 0 0 1 1 0 1 1 0 · The data for multiple blocks can be output sequentially in this mode.
I/O mode determined
For the CL normal high state
For the CL normal low state
Serial data input (IN1, IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75 µs tLC < 1.15µs tCE < 20 ms
CL: Normal high
Internal data
CL: Normal low
Internal data
Caution: The serial data I/O function can access data only after the crystal oscillator circuit is operating.
No. 5602-11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LC72720M.PDF ] | |
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