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PDF LC72366 Data sheet ( Hoja de datos )
| Número de pieza | LC72366 | |
| Descripción | Single-Chip PLL Microcontrollers | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : EN5065A
CMOS LSI
LC72358N, 72362N, 72366
Single-Chip PLL Microcontrollers
Overview
The LC72358N, LC72362N, and LC72366 are 1.33 µs
instruction execution time single-chip microcontrollers for
electronic tuning applications. These products incorporate
a high-speed locking circuit and a high-performance direct
PLL circuit that can control the local oscillator C/N
characteristics. These products have 256 or 512 bytes of
RAM and 16K, 24K or 32K bytes of program ROM on
chip, and incorporate a three-channel serial I/O interface,
a six-channel A/D converter and other interfaces.
Features
• ROM
— LC72358N: 8K steps (8191 × 16 bits)
— LC72362N: 12K steps (12287 × 16 bits)
— LC72366: 16K steps (16383 × 16 bits)
The subroutine area in both products is 4K steps
(4095 × 16 bits).
• RAM
— LC72358N, 72362N: 512 × 4 bits (banks 0 to 7)
— LC72366: 1K × 4 bits (banks 0 to F)
• Stack: Eight levels
• Serial I/O: Three channels (8-bit 3-wire format)
There are three internal serial clocks: 12.5 kHz,
37.5 kHz and 187.5 kHz.
• External interrupts:
Two channels (the INT0 and INT1 pins)
Switching between rising and falling edge detection is
supported.
• Internal interrupts:
Three channels
— Two internal timer interrupt channels
The timers provide eight interrupt periods: 100 µs,
1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms and 250 ms.
— One serial I/O interrupt channel
• Multiple interrupt levels:
Four levels
Hardware priority order
INT0 pin > INT1 pin > SI/O pin > internal timer 0 >
internal timer 1
• A/D converter: Six channels (6-bit successive approx-
imation type)
• General-purpose ports
— Input ports: 10
— Output ports: 28
— I/O ports: 25 (These pins can be switched between
input and output in bit units.)
• PLL block
— Built-in sub-charge pump for high-speed locking
— Support for dead zone control
— Built-in unlock detection circuit
— Twelve reference frequencies: 1, 3, 3.125, 5, 6.25, 9,
10, 12.5, 25, 30, 50 and 100 kHz
• Universal counter: 20 bits
Supports frequency and period
measurement with counting periods
of 1, 4, 8 and 32 ms.
• Timers: Timer interrupt periods
100 µs, 1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms
and 250 ms
• Beep: Six frequencies: 2.08 kHz, 2.25 kHz, 2.5 kHz,
3.0 kHz, 3.75 kHz, 4.17 kHz.
• Reset: Built-in voltage detection type reset circuit
• Cycle time: 1.33 µs (all instructions execute in one
cycle)
• Halt mode: The microcontroller operating clock is
stopped in halt mode.
There are four types of event that clear halt
mode: interrupt requests, timer FF
overflows, key inputs, and hold pin inputs.
• Operating supply voltage: 4.5 to 5.5 V (3.5 to 5.5 V
when only the controller
block operates)
• Package: QFP80E (QIP80E)
• OTP version: LC72P366
• Development tools: Emulator .................RE32N
Evaluation chip.......LC72EV350
Evaluation chip board
................................EB-72EV350
This LSI can easily use CCB that is SANYO’s original bus format.
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63096HA (OT)/62295TH (OT) No. 5065-1/13
1 page  
LC72358N, 72362N, 72366
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Conditions
Input high level current
IIH (1)
IIH (2)
IIH (3)
XIN: VI = VDD = 5.0 V
FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V
A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD,
HCTR, LCTR, with no pull-down resistor on A port.
VI = VDD = 5.0 V,
with the E, F, G, K, L, M and Q ports selected for input.
Input low level current
IIH (4)
IIL (1)
IIL (2)
IIL (3)
A port: pull-down resistor present, VI = VDD = 5.0 V
XIN: VI = VSS
FMIN, AMIN, HCTR, LCTR: VI = VSS
A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD,
HCTR, LCTR, with no pull-down resistor on A port.
VI = VSS,
with the E, F, G, K, L, M and Q ports selected for input.
Input floating voltage
VIF A port: pull-down resistor present
Pull-down resistance
RPD (1) A port: pull-down resistor present, VDD = 5 V
Hysteresis
VH F, G and K ports, LCTR (period measurement mode)
VOH (1) B and C ports: IO = –1 mA
Output high level voltage
VOH (2)
VOH (3)
D, E, F, G, K, L, M, N, O, P and Q ports: IO = –1 mA
EO1, EO2, EO3, SUBPD: IO = –500 µA
VOH (4) XOUT: IO = –200 µA
VOL (1) B and C ports: IO = 50 µA
VOL (2) D, E, F, G, K, L, M, N, O, P and Q ports: IO = 1 mA
Output low level voltage
VOL (3) EO1, EO2, EO3, SUBPD: IO = 500 µA
VOL (4) XOUT: IO = 200 µA
VOL (5) J port: IO = 5 mA
IOFF (1) B, C, D, E, F, G, K, L, M, N, O, P and Q ports
Output off leakage current
IOFF (2) EO1, EO2, EO3, SUBPD
IOFF (3) J port
A/D conversion error
ADI0 to ADI5: VDD (1)
Reject pulse width
PREJ
SNS
Power-down detection voltage
VDET
Pull-down resistance
RPD (2) TEST1, TEST2
IDD (1) VDD (1): fIN (2) = 130 MHz, Ta = 25°C
Current drain
IDD (2)
IDD (3)
VDD (2): Halt mode*, Ta = 25°C (Figure 1)
VDD = 5.5 V, oscillator stopped, Ta = 25°C (Figure 2)
IDD (4) VDD = 2.5 V, oscillator stopped, Ta = 25°C (Figure 2)
Note: Execute 20 STEP instructions every 1 ms. With the PLL, counters and other functions all stopped.
( ) Value: LC72366
Test Circuit
min
2.0
4.0
typ
5.0
10
50
2.0 5.0
4.0 10
75
0.1 VDD
VDD – 2.0
VDD – 1.0
VDD – 1.0
VDD – 1.0
100
0.2 VDD
VDD – 1.0
1.0
–3.0
–100
–5.0
–1/2
2.7
3.0
10
12
0.45
max
15
30
3.0
15
30
3.0
0.05 VDD
200
2.0
1.0
1.0
1.5
2.0
+3.0
+100
+5.0
+1/2
50
3.3
24
(0.9)
5
1
Unit
µA
µA
µA
µA
µA
µA
µA
V
kΩ
V
V
V
V
V
V
V
V
V
V
µA
nA
µA
LSB
µs
V
kΩ
mA
mA
µA
µA
Note: All of the pins PB to PG and PJ to PQ must be left open.
Here, the pins PE to PG, PK to PM, and PQ are selected for output.
Figure 1: IDD(2) in Halt Mode
Note: All of the pins PA to PQ must be left open.
Figure 2. IDD(3) and IDD(4) in Backup Mode
No. 5065-5/13
5 Page 
LC72358N, 72362N, 72366
LC72358N, LC72362N and LC72366 Instruction Table
Abbreviations:
ADDR: Program memory address
b: Borrow
C: Carry
DH: Data memory address high (row address): 2 bits
DL: Data memory address low (column address):4 bits
I: Immediate data:4 bits
M: Data memory address
N: Bit position
Pn: Port number:4 bits
PWn: Port control word number: 4 bits
r: General register (one of banks 00 to 0FH)
Rn: Register number:4 bits
( ): Contents of register or memory
( )N: Contents of bit N of register or memory
Operand
Mnemonic
1st 2nd
Function
AD
ADS
AC
ACS
AI
AIS
AIC
AICS
SU
SUS
SB
SBS
SI
SIS
SIB
SIBS
r M Add M to r
Add M to r,
r M then skip if carry
r M Add M to r with carry
Add M to r with carry,
r M then skip if carry
M I Add I to M
Add I to M,
M I then skip if carry
M I Add I to M with carry
Add I to M with carry,
M I then skip if carry
r M Subtract M from r
Subtract M from r,
r M then skip if borrow
Subtract M from r with
r M borrow
Subtract M from r with
r M borrow,
then skip if borrow
M I Subtract I from M
Subtract I from M,
M I then skip if borrow
Subtract I from M with
M I borrow
Subtract I from M with
M I borrow,
then skip if borrow
SEQ
r M Skip if r equal to M
SEQI
M I Skip if M equal to I
SNEI
M I Skip if M not equal to I
SGE
SGEI
SLEI
r M Skip if r is greater
than or equal to M
M I Skip if M is greater
than or equal to I
M I Skip if M is less than I
Operation
r ← (r) + (M)
r ← (r) + (M)
skip if carry
r ← (r) + (M) + C
r ← (r) + (M) + C
skip if carry
M ← (M) + I
M ← (M) + I
skip if carry
M ← (M) + I + C
M ← (M) + I + C
skip if carry
r ← (r) – (M)
r ← (r) – (M)
skip if borrow
r ← (r) – (M) – b
r ← (r) – (M) – b
skip if borrow
M ← (M) – I
M ← (M) – I
skip if borrow
M ← (M) – I – b
M ← (M) – I – b
skip if borrow
(r) – M
skip if zero
(M) – I
skip if zero
(M) – I
skip if not zero
(r) – M
skip if not borrow
(M) – I
skip if not borrow
(M) – I
skip if zero
Machine code
D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0
0 1 0 0 0 0 DH
DL
r
0100
0100
0100
0101
0101
0101
0101
0110
0110
01
10
11
00
01
10
11
00
01
DH
DH
DH
DH
DH
DH
DH
DH
DH
DL
DL
DL
DL
DL
DL
DL
DL
DL
r
r
r
I
I
I
I
r
r
0 1 1 0 1 0 DH
DL
r
0 1 1 0 1 1 DH
0111
0111
00
01
DH
DH
0 1 1 1 1 0 DH
DL
DL
DL
DL
r
I
I
I
0 1 1 1 1 1 DH
DL
I
0 0 0 1 0 0 DH
0 0 0 1 0 1 DH
0 0 0 0 0 1 DH
DL
DL
DL
r
I
I
0 0 0 0 1 1 DH
DL
r
0 0 0 1 1 1 DH
0 0 0 0 1 1 DH
DL I
DL I
Continued on next page.
No. 5065-11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet LC72366.PDF ] | |
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