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Datasheet LC72191JM PDF ( 特性, スペック, ピン接続図 )

部品番号 LC72191JM
部品説明 PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 
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LC72191JM Datasheet, LC72191JM PDF,ピン配置, 機能
Ordering number : EN 3985C
CMOS LSI
LC72191, 72191M, 72191JM
PLL Frequency Synthesizer
for Electronic Tuning in Car Stereo Tuners
Overview
The LC72191, LC72191M and LC72191JM are PLL
frequency synthesizers for electronic tuning. The
LC72191, LC72191M and LC72191JM are optimal for
AM/FM tuner circuits that require high mounting
densities.
Features
Designed for use in car stereos, the LC72191 provides a
rich set of reference frequencies, I/O ports, a general-
purpose counter, and an unlock detection circuit.
Functions
• Programmable dividers
— FMIN pin: 130 MHz at 70 mVrms and 160 MHz at
100 mVrms input (built-in prescaler)
— AMIN pin: Pulse swallower and direct division
techniques
• Reference frequencies: Ten selectable frequencies:
1, 5, 9, 10, 3.125, 6.25, 12.5 25, 50 and 100 kHz
• Output ports: 7 pins
Complementary outputs: 2 pins
N-channel open drain outputs: 5 pins
• Input ports: 2 pins
• General-purpose counter: For measuring IF and other
signals (Also used for station detection when
functioning as an IF counter.)
— HCTR pin: Frequency measurement (for inputs up to
70 MHz)
— LCTR pin: Frequency and period measurement
• PLL unlock detection circuit
Detects phase differences of 0.55, 1.11, 2.22 and 3.33 µs.
• Controller clock output: 400 kHz
• Clock time base output: 8 Hz
• Serial data I/O
— Supports CCB format communication with the
system controller.
• Package: LC72191: DIP24S
LC72191M: MFP24
LC72191JM: MFP24S
Package Dimensions
unit: mm
3067-DIP24S
[LC72191]
SANYO: DIP24S
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D3096HA (OT)/D2593JN/6182JN No. 3985-1/16

1 Page



LC72191JM pdf, ピン配列
Block Diagram
LC72191, 72191M, 72191JM
Pin Symbols
XIN, XOUT: Crystal oscillator (7.2 MHz)
FMIN, AMIN: Local oscillator signal input
CE, CL, DI, DO: Serial data I/O
OUT0 to OUT6: Output ports
IN0, IN1:
Input ports
HCTR, LCTR: General-purpose counter inputs
PD1, PD2:
Charge pump outputs
SYC:
Control clock (400 kHz)
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN (1)
VIN (2)
VOUT (1)
VOUT (2)
VOUT (3)
VOUT (4)
Pd max
Topr
Tstg
Conditions
VDD
CE, CL, DI, IN0, IN1
Input pins other than VIN (1)
DO, SYC
OUT1, OUT2
OUT3 to OUT6, OUT0
Output pins other than VOUT (1), VOUT (2) and VOUT (3)
Ta 85°C
:LC72191
:LC72191M
:LC72191JM
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to VDD + 0.3
–0.3 to +7.0
–0.3 to VDD + 0.3
–0.3 to +15
–0.3 to VDD + 0.3
350
300
200
–40 to +85
–55 to +125
Unit
V
V
V
V
V
V
V
mW
°C
°C
No. 3985-3/16


3Pages


LC72191JM 電子部品, 半導体
LC72191, 72191M, 72191JM
Pin Functions
Pin No. Symbol
1 XIN
24 XOUT
I/O
Input
Output
Type
Xtal OSC
19 FMIN
Input
Local oscillator signal
input
18 AMIN
Input
Local oscillator signal
input
Function
• Connections for a 7.2 MHz crystal oscillator
• FMIN is selected when DV in the serial input data is set to 1.
• Input frequency range: 10 to 130 MHz (70 mVrms minimum)
• The signal passes through an internal divide-by-two prescaler and is then supplied to
the swallow counter.
• Although the divisor setting is in the range 256 to 65,536, the actual divisor will be twice
the set value due to the presence of the internal divide-by-two prescaler.
• AMIN is selected when DV in the serial input data is set to 0.
• When SP in the serial input data is set to 1:
— Input frequency range: 2 to 40 MHz (70 mVrms minimum).
— The signal is supplied directly to the swallow counter without passing through the
internal divide-by-two prescaler.
— The divisor setting is in the range 256 to 65,536 and the actual divisor will be the
value set.
• When SP in the serial input data is set to 0:
— Input frequency range: 0.5 to 10 MHz (70 mVrms minimum).
— The signal is supplied directly to a 12-bit programmable divider.
— The divisor setting is in the range 4 to 4,096 and the actual divisor will be the
value set.
• PLL charge pump outputs. High levels are output from PD1 and PD2 when the local
21
22
PD1
PD2
Three-state Charge pump outputs
oscillator frequency divided by n is higher than the reference frequency, and low levels
are output when that frequency is lower than the reference frequency.
These pins go to the floating state when the frequencies agree.
6
SYC
N-channel
open drain
Controller clock
20 VDD
— Power supply
23 VSS
— Ground
2 CE Input*1 Chip enable
4 CL Input*1 Clock
• SYC is a controller clock source. The LC72191 outputs a 400 kHz 66% duty signal
from this pin after power is applied.
• The LC72191 power supply pin. A voltage of between 4.5 and 6.5 V must be provided
when the PLL is operating. The supply voltage can be lowered to 3.5 V when only
operating the crystal oscillator circuit to acquire the controller clock and the clock time
base outputs.
• The LC72191 ground pin
• This pin must be set high when inputting serial data (via DI) or when outputting serial
data (via DO).
• The clock input used for data signal synchronization during serial data input (via DI) or
output (via DO).
3 DI Input*1 Input data
• Input pin used when transferring serial data from the controller to the LC72191.
• A total of 36 bits of data must be supplied to set up the LC72191 initial state.
Output
5 DO (N-channel Output data
open drain)
• Output pin used when transferring serial data to the controller from the LC72191.
• A total of 28 bits from an internal shift register can be output in synchronization with the
CL signal.
9 OUT0
10 OUT1
11 OUT2
12
OUT3
Output*2 Output port
13 OUT4
14 OUT5
17 OUT6
• These pins latch bits O0 to O6 in the serial data transferred from the controller, invert
that data and output the inverted data in parallel.
• The OUT0 pin can also be used to output an 8 Hz clock time base signal.
(When TB is 1.)
• OUT1 and OUT2 are complementary outputs.
• OUT0, OUT3, OUT4, OUT5 and OUT6 are N-channel open drain outputs that can
handle up to 13 V.
Note: *1. The high and low level input voltages for the CE, CL, DI, IN0 and IN1 pins are VIH = 2.2 to 6.5 V and VIL = 0 to 0.7 V, regardless of the power
supply voltage VDD.
*2. Since the output port states are undefined when power is first applied, transfer the control data quickly.
Continued on next page.
No. 3985-6/16

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