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Datasheet LC7215 PDF ( 特性, スペック, ピン接続図 )

部品番号 LC7215
部品説明 MW/LW PLL Frequency Synthesizers
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 
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LC7215 Datasheet, LC7215 PDF,ピン配置, 機能
Ordering number: EN 3584B
Silicon-gate CMOS LSI
LC7215, 7215F, 7215FM
MW/LW PLL Frequency Synthesizers
Overview
The LC7215, LC7215F and LC7215FM are phase-locked-loop
frequency synthesizer LSIs that provide accurate reference
frequencies over the MW and LW bands, making them ideally
suited for AM tuners.
Package Dimensions
unit : mm
3003A-DIP14
[LC7215, 7215F]
Features
. PLL frequency synthesizer LSIs for MW and LW bands.
. Reference frequencies of 1, 5, 9 and 10 kHz.
. On-chip transistor for the low-pass filter amplifier.
. Single output pin (CMOS output)
. Controller clock output pin.
. Time-base output pin.
. All devices can be used for double conversion demodulation.
. The LC7215F and 7215FM have expanded input frequency
ranges.
LC7215
0.5 to 13 MHz : (DIP14)
LC7215F/FM 0.5 to 20 MHz : (DIP14/MFP14S)
unit : mm
3111-MFP14S
SANYO : DIP14
[LC7215FM]
SANYO : MFP14S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D2597HA(II)/1291JN/7200JN No.3584-1/7

1 Page



LC7215 pdf, ピン配列
LC7215, 7215F, 7215FM
Electrical Characteristics within the allowable operating ranges
Values in parentheses are for LC7215F and LC7215FM.
Parameter
High-level input currents
Low-level input currents
High-level output voltages
Low-level output voltages
Output off-state leakage
currents
Tristate output High-level
off-state leakage current
Tristate output Low-level
off-state leakage current
High-level output voltage
Low-level output voltage
Symbol
IIH1
IIH2
IIH3
IIH4
IIL1
IIL2
IIL3
IIL4
VOH1
VOH2
VOL1
VOL2
VOL4
VOL5
IOFF1
IOFF2
IOFFH
IOFFL
VOH3
VOL3
IDD1
Supply current
IDD2
IDD3
* S, O and P are serial control bits.
Conditions
XIN: VI = VDD
PIN: VI = VDD
CE, CL, DATA: VI = VDD
AIN: VI = VDD
XIN: VI = VSS
PIN: VI = VSS
CE, CL, DATA: VI = VSS
AIN: VI = VSS
DOUT: IO = 1 mA
PDOUT: IO = 0.5 mA
DOUT: IO = –1 mA
PDOUT: IO = –0.5 mA
SYC, TB: IO = 0.5 mA
AOUT: IO = 1 mA
SYC, TB: VO = VDD
AOUT: VO = 13 V
PDOUT: VO = VDD
PDOUT: VO = VSS
XOUT: IO = –0.1 mA
XOUT: IO = 0.1 mA
VDD: fIN1 = 13 MHz, *S = 1 (High speed)
(Note 1)
fIN1 = 20 MHz, *S = 1 (High speed)
(Note 1)
VDD: fIN1 = 2.5 MHz, *S = 0 (Low speed)
(Note 1)
VDD: VDD = 5.5 V, *O = 0, P = 1 (Note 2)
VDD = 4.5 V, *O = 0, P = 1 (Note 2)
VDD = 3.0 V, *O = 0, P = 1 (Note 2)
min typ max Unit
20 µA
40 µA
3.0 µA
0.01 1.0 µA
20 µA
40 µA
3.0 µA
0.01 1.0 µA
VDD
–1.0
V
VDD
–1.0
V
1.0 V
1.0 V
1.0 V
1.0 V
3.0 µA
5.0 µA
0.01 1.0 nA
0.01 1.0 nA
VDD
–1.0
V
1.0 V
10 mA
(12) mA
5 mA
1.2 2.0 mA
0.7 1.5 mA
0.4 1.0 mA
Note 1. VIN1 = VIN2 = 100 mVms. The 11.16 MHz crystal is connected to XIN and XOUT. All other inputs are connected to VSS
and all other outputs are open.
2. The 11.16 MHz crystal is connected to XIN and XOUT. All other inputs are connected to VDD and all other outputs are
open. (Backup mode when PLL is halted.)
Pin Assignment
No.3584-3/7


3Pages


LC7215 電子部品, 半導体
Data Input Timing
VIH = 2.0 to VDD, VIL = 0 to 0.5 V
X’tal = 8.00 to 11.16 (typ) to 12.00 MHz
Data latch: Rising edge of CL
LC7215, 7215F, 7215FM
Item
Enable setup time
Enable hold time
Data setup time
Data hold time
Clock Low-level time
Clock High-level time
Rise time
Fall time
Symbol
tES
tEH
tSU
tHD
tLO
tHI
tR
tF
11.16 MHz crystal
At least 12 µs
1 µs or less
Other crystal frequencies
At least 2 × (1/fXtal × 62)
1 µs or less
Effective value
1/2 of the value
shown at left
No.3584-6/7

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