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Datasheet LC72137M PDF ( 特性, スペック, ピン接続図 )

部品番号 LC72137M
部品説明 PLL Frequency Synthesizer for Electronic Tuning
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 
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LC72137M Datasheet, LC72137M PDF,ピン配置, 機能
Ordering number : EN5743
CMOS IC
LC72137, 72137M
PLL Frequency Synthesizer
for Electronic Tuning
Overview
The LC72137 and LC72137M are PLL frequency
synthesizers for use in radio/cassette players. They allow
high-performance AM/FM tuners to be implemented
easily.
Features
• High-speed programmable frequency divider
— FMIN: 10 to 160 MHz.....Pulse swallower
(divide-by-two prescaler built in)
— AMIN: 2 to 40 MHz.........Pulse swallower
0.5 to 10 MHz......Direct division
• IF counter
IFIN: 0.4 to 12 MHz................For use as an AM/FM IF
counter
• Reference frequency
— Selectable from one of eight frequencies (crystal
oscillator: 75 kHz)
1, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz
• Phase comparator
— Supports dead zone control
— Built-in unlock detection circuit
— Built-in deadlock clear circuit
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports
— Dedicated output ports: 4
— I/O ports: 2
— Supports clock time base output
• Serial Data I/O
— Supports CCB format communication with the
system controller.
• Operating ranges
— Supply voltage: 2.5 to 3.6 V
— Operating temperature: –20 to +70°C
• Packages
—DIP22S/MFP20
Package Dimensions
unit: mm
3059-DIP22S
[LC72137]
unit: mm
3036B-MFP20
[LC72137M]
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO: DIP22S
SANYO: MFP20
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
70398RM(OT) No. 5743-1/23

1 Page



LC72137M pdf, ピン配列
LC72137, 72137M
Electrical Characteristics within the allowable operating ranges
Parameter
Internal feedback resistors
Internal pull-down resistors
Internal output resistor
Hysteresis
Output high-level voltage
Output low-level voltage
Input high-level voltage
Input low-level current
Output off leakage current
High-level three-state off
leakage current
Low-level three-state off
leakage current
Input capacitance
Current drain
Symbol
Conditions
Rf1
Rf2
Rf3
Rf4
Rpd1
Rpd2
Rd
VHIS
VOH1
VOL1
VOL2
VOL3
VOL4
IIH1
IIH2
IIH3
IIH4
IIH5
IIH6
IIL1
IIL2
IIL3
IIL4
IIL5
IIL6
IOFF1
IOFF2
IOFFH
XIN
FMIN
AMIN
IFIN
FMIN
AMIN
XOUT
CE, CL, DI, IO1, IO2
PD: IO = –1 mA
PD: IO = 1 mA
BO1 to BO4, IO1, IO2; IO = 1 mA
BO1 to BO4, IO1, IO2; IO = 5 mA
DO: IO = 1 mA
AOUT, AIN = 1.3 V
CE, CL, DI: VI = 6.5 V
IO1, IO2: VI = 13 V
XIN: VI = VDD
FMIN, AMIN: VI = VDD
IFIN: VI = VDD
AIN: VI = 6.5 V
CE, CL, DI: VI = 0 V
IO1, IO2: VI = 0 V
XIN: VI = 0 V
FMIN, AMIN: VI = 0 V
IFIN: VI = 0 V
AIN: VI = 0 V
BO1 to BO4, AOUT, IO1, IO2: VO = 13 V
DO: VO = 6.5 V
PD: VO = VDD
min
VDD – 1.0
Ratings
typ
8.0
500
500
250
200
200
250
0.1 VDD
0.16
2.5
5.0
0.16
2.5
5.0
0.01
IOFFL
CIN
IDD1
IDD2
IDD3
PD: VO = 0 V
FMIN
VDD: Xtal = 75 kHz, fIN2 = 130 MHz, VIN2 = 20 mVrms
VDD: PLL block stopped (PLL inhibit),
Xtal oscillator operating (Xtal = 75 kHz)
VDD: PLL block stopped, Xtal oscillator stopped
0.01
6
2.5
20
max
1.0
0.25
1.25
0.25
0.5
5.0
5.0
0.9
15
30
200
5.0
5.0
0.9
15
30
200
5.0
5.0
200
200
6
10
Unit
M
k
k
k
k
k
k
V
V
V
V
V
V
µA
µA
µA
µA
µA
nA
µA
µA
µA
µA
µA
nA
µA
µA
nA
nA
pF
mA
mA
µA
No. 5743-3/23


3Pages


LC72137M 電子部品, 半導体
Pin Descriptions
Symbol
Pin No.
(MFP pin numbers
are in parentheses.)
Type
LC72137, 72137M
Functions
XIN
XOUT
20 (19)
21 (21)
Xtal
• Crystal oscillator connections (75 kHz)
Circuit configuration
FMIN
13 (12)
Local oscillator
signal input
• FMIN is selected when the serial data input DVS bit is
set to 1.
• The input frequency range is from 10 to 160 MHz.
• The input signal passes through the internal divide-by-
two prescaler and is input to the swallow counter.
• The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.
AMIN
12 (11)
Local oscillator
signal input
• AMIN is selected when the serial data input DVS bit is
set to 0.
• When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
— The divisor can be in the range 272 to 65535, and
the divisor used will be the value set.
• When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable
divider.
— The divisor can be in the range 4 to 4095, and the
divisor used will be the value set.
CE
2 (1)
Chip enable
• Set this pin high when inputting (DI) or outputting (DO)
serial data.
DI
3 (2)
Input data
• Inputs serial data transferred from the controller to the
LC72137.
CL
4 (3)
Clock
• Used as the synchronization clock when inputting (DI) or
outputting (DO) serial data.
• Outputs serial data transferred from the LC72137 to the
DO
5 (4)
Output data
controller. The data output is determined by the DOC0 to
DOC2 bits in the serial data.
• The LC72137 power supply pin. (VDD = 2.5 to 3.6 V)
VDD
15 (14)
Power supply
• The power on reset circuit operates when power is first
applied.
VSS
16 (15)
Ground
• The LC72137N ground
Continued on next page.
No. 5743-6/23

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