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PDF LC72131M Data sheet ( Hoja de datos )
| Número de pieza | LC72131M | |
| Descripción | AM/FM PLL Frequency Synthesizer | |
| Fabricantes | Sanyo Semicon Device | |
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Ordering number : EN4921B
CMOS LSI
LC72131, 72131M
AM/FM PLL Frequency Synthesizer
Overview
The LC72131 and LC72131M are PLL frequency
synthesizers for use in tuners in radio/cassette players.
They allow high-performance AM/FM tuners to be
implemented easily.
Applications
Package Dimensions
unit: mm
3059-DIP22S
[LC72131]
PLL frequency synthesizer
Functions
• High speed programmable dividers
— FMIN: 10 to 160 MHz ..........pulse swallower
(built-in divide-by-two prescaler)
— AMIN: 2 to 40 MHz ..............pulse swallower
0.5 to 10 MHz ...........direct division
• IF counter
— IFIN: 0.4 to 12 MHz ...........AM/FM IF counter
• Reference frequencies
— Twelve selectable frequencies
(4.5 or 7.2 MHz crystal)
1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50 and 100 kHz
• Phase comparator
— Dead zone control
— Unlock detection circuit
— Deadlock clear circuit
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports
— Dedicated output ports: 4
— Input or output ports: 2
— Support clock time base output
• Serial data I/O
— Support CCB format communication with the
system controller.
• Operating ranges
— Supply voltage........................4.5 to 5.5 V
— Operating temperature............–40 to +85°C
• Packages
— DIP22S/MFP20
unit: mm
3036B-MFP20
[LC72131M]
SANYO: DIP22S
SANYO: MFP20
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
62096HA (OT)/O3195HA (OT)/92294TH (OT) No. 4921-1/23
1 page  
LC72131, 72131M
Electrical Characteristics for the Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V
Parameter
Built-in feedback resistance
Built-in pull-down resistor
Hysteresis
Output high level voltage
Output low level voltage
Input high level current
Input low level current
Output off leakage current
High level three-state
off leakage current
Low level three-state
off leakage current
Input capacitance
Current drain
Symbol
Rf1
Rf2
Rf3
Rf4
Rpd1
Rpd2
VHIS
VOH1
VOL1
Pins
XIN
FMIN
AMIN
IFIN
FMIN
AMIN
CE, CL, DI, IO1, IO2
PD
PD
VOL2 BO1
VOL3 DO
VOL4 BO2 to BO4, IO1, IO2
VOL5
IIH1
IIH2
IIH3
IIH4
IIH5
IIH6
IIL1
IIL2
IIL3
IIL4
IIL5
IIL6
IOFF1
IOFF2
IOFFH
IOFFL
CIN
IDD1
AOUT
CE, CL, DI
IO1, IO2
XIN
FMIN, AMIN
IFIN
AIN
CE, CL, DI
IO1, IO2
XIN
FMIN, AMIN
IFIN
AIN
BO1 to BO4, AOUT,
IO1, IO2
DO
PD
PD
FMIN
VDD
IDD2
VDD
IDD3
VDD
Conditions
IO = –1 mA
IO = 1 mA
IO = 0.5 mA
IO = 1 mA
IO = 1 mA
IO = 5 mA
IO = 1 mA
IO = 5 mA
IO = 8 mA
IO = 1 mA, AIN = 1.3 V
VI = 6.5 V
VI = 13 V
VI = VDD
VI = VDD
VI = VDD
VI = 6.5 V
VI = 0 V
VI = 0 V
VI = 0 V
VI = 0 V
VI = 0 V
VI = 0 V
VO = 13 V
VO = 6.5 V
VO = VDD
VO = 0 V
Xtal = 7.2 MHz,
fIN2 = 130 MHz,
VIN2 = 40 mVrms
PLL block stopped
(PLL INHIBIT),
Xtal oscillator operating
(Xtal = 7.2 MHz)
PLL block stopped
Xtal oscillator stopped
min
VDD – 1.0
typ
1.0
500
500
250
200
200
0.1 VDD
2.0
4.0
8.0
2.0
4.0
8.0
0.01
0.01
6
5
max
1.0
0.5
1.0
0.2
1.0
0.2
1.0
1.6
0.5
5.0
5.0
11
22
44
200
5.0
5.0
11
22
44
200
5.0
5.0
200
200
10
0.5
10
Unit
MΩ
kΩ
kΩ
kΩ
kΩ
kΩ
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
nA
µA
µA
µA
µA
µA
nA
µA
µA
nA
nA
pF
mA
mA
µA
No. 4921-5/23
5 Page 
LC72131, 72131M
Continued from preceding page.
No. Control block/data
DO pin control data
DOC0, DOC1, DOC2
Functions
• Data that determines the DO pin output
DOC2
0
0
0
0
1
1
1
1
DOC1
0
0
1
1
0
0
1
1
DOC0
0
1
0
1
0
1
0
1
DO pin state
Open
Low when the unlock state is detected
end-UC*1
Open
Open
The IO1 pin state*2
The IO2 pin state*2
Open
The open state is selected after the power-on reset.
Note: 1. end-UC: Check for IF counter measurement completion
(6)
Related data
UL0, UL1,
CTE,
IOC1, IOC2
Unlock detection data
UL0, UL1
(7)
Phase comparator
control data
DZ0, DZ1
(8)
When end-UC is set and the IF counter is started (i.e., when CTE is changed
from zero to one), the DO pin automatically goes to the open state.
When the IF counter measurement completes, the DO pin goes low to indicate
the measurement completion state.
Depending on serial data I/O (CE: high) the DO pin goes to the open state.
2. Goes to the open state if the I/O pin is specified to be an output port.
Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE
high) will be open, regardless of the state of the DO control data (DOC0 to DOC2).
Also, the DO pin during a data output period (an OUT mode period with CE high)
will output the contents of the internal DO serial data in synchronization with the
CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2).
• Selects the phase error (øE) detection width for checking PLL lock.
A phase error in excess of the specified detection width is seen as an unlocked state.
UL1 UL0
øE detection width
Detector output
0 0 Stopped
Open
0 10
øE is output directly
1 0 ±0.55 µs
øE is extended by 1 to 2 ms
1 1 ±1.11 µs
øE is extended by 1 to 2 ms
Note: In the unlocked state the DO pin goes low and the UL bit in the serial data
becomes zero.
• Controls the phase comparator dead zone.
DOC0,
DOC1,
DOC2
DZ1 DZ0
0 0 DZA
0 1 DZB
1 0 DZC
1 1 DZD
Dead zone mode
Dead zone widths: DZA < DZB < DZC < DZD
Clock time base
(9) TBC
Setting TBC to one causes an 8 Hz, 40% duty clock time base signal to be output
from the BO1 pin. (BO1 data is invalid in this mode.)
BO1
Charge pump control data • Forcibly controls the charge pump output.
DLC
DLC
Charge pump output
0 Normal operation
(10) 1 Forced low
Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO
oscillator stopping, deadlock can be cleared by forcing the charge pump output to
low and setting Vtune to VCC. (This is the deadlock clearing circuit.)
Continued on next page.
No. 4921-11/23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet LC72131M.PDF ] | |
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