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PDF ISL55112 Data sheet ( Hoja de datos )
| Número de pieza | ISL55112 | |
| Descripción | High-Speed Dual Precision CCD Driver | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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High-Speed Dual Precision CCD Driver
ISL55112
The ISL55112 is a high-speed CCD array driver
comprising 2 Horizontal drivers with high current output
drive and 2 ancillary signal drivers with lower current
output drive.
The devices can be used in pairs to drive and control two
halves of a high pixel count CCD array as used in high
end Digital Cameras or Camcorders. The device has a
largely symmetric pinout about a center axis to facilitate
the placement of the devices on either side of a large
CCD array with minimal signal routing disruption.
The ISL55112 can accommodate split asymmetric
voltage supplies up to 8V total for each of the 4 drivers
and has significant flexibility in the selection of these
supply voltages within this range. All 4 drivers have their
own High and Low level supply lines to minimize
interference between drivers caused by shared current
paths.
Special circuitry for the high current drivers is included to
ensure the highest degree of stability of the driver output
resistance over varying supply voltage, temperature and
semiconductor process variations, resulting in highly
consistent, predictable waveform crossover points.
The ISL55112 can drive high capacitance loads at pixel
clock rates exceeding 30MHz with low propagation
delays, and skews between channels of better than
±500ps.
The ISL55112 is available in 24 Ld exposed pad TQFN
package and is specified for operation over the full -40°C
to +85°C temperature range.
Features
• 2 Horizontal Row Drivers (High Current)
• 2 Ancillary Drivers (Lower Current)
• Up to 8V Signal Swing
• Unipolar and Bipolar Supply Capability
• Adjustable Output Impedance for EMI Control
• 3V Logic Interface
• Low Propagation Delays
• Low Skew: ±500ps
• High Clock Rates: 30MHz+
• Stand-by and Power-Down Modes
Applications*(see page 19)
• Digital Still Cameras
• High Definition Digital Camcorders
• Industrial Vision Systems
• Medical Imaging
• Semiconductor Wafer and Mask Inspection
Equipment
• High Definition Security Systems
• Home Security Systems
Pin Configuration
ISL55112
(24 LD TQFN)
TOP VIEW
Ordering Information
PART
TEMP.
NUMBER
PART RANGE PACKAGE PKG.
(Notes 1, 2, 3) MARKING (°C) (Pb-Free) DWG. #
ISL55112IRTZ 55112 IRTZ -40 to +85 24 Ld TQFN L24.4x5C
1. Add “-T” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die
attach materials and 100% matte tin plate plus anneal (e3
termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device
information page for ISL55112. For more information on
MSL please see techbrief TB363.
24 23 22 21 20
RGIN 1
H1IN 2
PD 3
ROIC 4
EN 5
H2IN 6
HLIN 7
19 H1_VN
18 H1_OUT
17 H1_VP
16 DNC
15 H2_VP
14 H2_OUT
13 H2_VN
8 9 10 11 12
September 23, 2009
FN6649.0
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL55112
Electrical Specifications
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4wVw, VwS.DUaBta=Sh-4eVe,t4U.com
ROIC = 68kΩ; Unless Otherwise specified. Full (-40°C to +85°C) limits are established by
characterization and are not production tested. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8)
TEMP
MIN
(°C) (Note 6)
TYP
MAX
(Note 6) UNITS
LOGIC INPUT CHARACTERISTICS EN (Enable) and PD (Power-Down) DRIVER INPUT
VIH Input High Threshold Voltage EN, PD
(Note 11)
VDD = 3.3V
25 2.0
Full 2.0
V
V
VIL Input Low Threshold Voltage EN, PD
(Note 11)
VDD = 3.3V
25
Full
1.2 V
1.2 V
IIH Logic “1” Input Current
EN, PD
VINPUT = 5.5V,
VDD = 5.5V
25
Full
3 5 µA
5.5 µA
IIL Logic “0” Input Current
EN, PD
VINPUT = 0.0V,
VDD = 5.5V
25
Full
45 nA
50 nA
CIN Input Capacitance (Gnd)
EN, PD
RIN Input Resistance (Gnd)
EN, PD
DRIVER SIGNAL OUTPUT CHARACTERISTICS H1 and H2 (Note 12)
25
25
3.5 pF
2M Ω
VOH Driver Output High Voltage H1, H2: IOUT = -10mA
25
3.9
3.93
3.95
V
VOL Driver Output Low Voltage H1, H2 IOUT = 10mA
25
-3.95
-3.93
-3.90
V
ROH
Driver Source Output
Resistance
H1, H2: IOUT = -100mA (Note
12)
25
2.8 9
Ω
ROL Driver Sink Ouput
Resistance
H1, H2: IOUT = -100mA
(Note 12)
25
2.0 8
Ω
IPK+ Peak Sourcing Current
IPK- Peak Sinking Current
tR Driver Rise Time
H1, H2:
ROIC = 40k
CL = 0.022µf,
(Notes 12,13)
ROIC = 68k
ROIC = 80k
ROIC = 120k
H1, H2:
ROIC = 40k
CL = 0.022µf,
(Notes 12,13)
ROIC = 68k
ROIC = 80k
ROIC = 120k
H1, H2: CL = 300pF: VP = +6V,
VN = -1V
25
25
25
25
25
25
25
25
25
Full
2.66
2.04
1.96
1.66
2.18
1.72
1.64
1.52
2.8
4.2
4.3
Α
Α
Α
Α
Α
Α
Α
Α
ns
ns
tF Driver Fall Time
H1, H2: CL = 300pF: VP = +6V,
VN = -1V
25
Full
2.8 4.2
4.3
ns
ns
tPD+
Propagation Delay Rising
Edge
H1, H2: CL = 300pF: VP= +6V,
VN = -1V
25
Full
7.7 10.1
10.5
ns
ns
tPD-
Propagation Delay Falling
Edge
H1, H2: CL = 300pF: VP= +6V,
VN = -1V
25
Full
7.7 10.1
10.5
ns
ns
tSKEW+ Driver Skew, H1 to H2 Rising H1, H2: CL = 300pF
Edge
25 0 ns
Full -0.50
0.50
ns
tSKEW- Driver Skew, H1 to H2 Falling H1, H2: CL = 300pF
Edge
25 0 ns
Full -0.50
0.50
ns
tSKEW± Skew: H1 Rising H2 Falling H1, H2: CL = 300pF
25 0 ns
Full -0.50
0.50
ns
5 FN6649.0
September 23, 2009
5 Page 
ISL55112
power inputs have settled but should not be allowed to
float during power-up and power-down operations.
Note: If VSUB floats high when VDD is applied, a 10k to
50k Resistor should be added from VSUB to ground. For
proper power up biasing, VSUB should not be allowed to
float high when only VDD is applied.
Power Supply Bypassing and Printed Circuit
Board Layout
Maximum current occurs during edge-transition of the
driver outputs. Decoupling of the VP and VN rails for the
drivers is of paramount concern. This being especially
true of the high current drivers. Minimum possible lead
length from the VP/VN device connections to the
associated decoupling capacitors is key to device
performance.
Given transition times are the point of maximum current,
series inductance from the decoupling point to the VP/
VN connections and from the VOUT connection to the
CCD should be kept to the minimum possible values.
Note: The ISL55112 employs multiple bond wires on all
driver rail and driver output connections. Multiple bond
wires help reduce the device package internal bond wire
connection inductance.
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible, and the power
supply pins must be well bypassed to reduce the risk of
oscillation.
The “Evaluation Board” drawing depicts a conceptual
decoupling scenario. Capacitor values, placement and
quantities are subject to specific application
requirements. The key to decoupling, especially during
edge transitions, is to reduce the series inductance of the
VP/VN supply rails.
Decoupling Discussion and
Evaluation Board Information
• With split supply driver voltages, each VN and VP pin
should have a separate 0.1µF capacitor to ground.
The capacitors should be on the top layer of the PCB
to a ground plane. This avoids the operative
decoupling point having a via in series with the
device pin.
• Single supply applications require fewer decoupling
capacitors (VN rails are connected to ground. In this
case, the top layer should also be a ground plane
and VP pins should be decoupled as closely as
possible.
• In both cases, the return path series inductance
needs to be considered. The return current path of
the load and the decoupled point should be as close
as possible. Avoid/reduce Vias between driver rail
decoupling points and driver output to load.
Figure 5 shows the top decoupling provides the high
frequency driver rail decoupling during edge transitions
(C1, C4, C6, C11). Figure 6 showswvwiwas.DbaetatwSheeeent4bUo.cttoomm
decoupling and the device pins on top increase series
inductance. However, bottom decoupling replenishes the
top decoupling before and after edge currents occur.
Additional bulk decoupling (22µF to 4.7µF) should also be
used. This is low frequency decoupling and need not be
located as close to the output area of the device.
FIGURE 5. TOP COMPONENT AND PCB ARTWORK
FIGURE 6. BOTTOM COMPONENT AND PCB ARTWORK
Output Impedance Control (OIC)
An external Resistor, ROIC, is used to set the output
impedance of the high current drivers. Selection of ROIC
resistance value enables the user to adjust high current
H1/H2 driver operation for a specific CCD product.
Rise and Fall times can be adjusted via the ROIC
resistance setting. This is accomplished by selecting an
ROIC resistance value from 40kΩ to 120kΩ. Actual
rise/fall timing will be the product of driver loading and
interconnect parasitics.
High current driver characteristics, which are normally
affected by temperature and process variations, are kept
to a minimum by the ISL55112 OIC feature.
11 FN6649.0
September 23, 2009
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL55112.PDF ] | |
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