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PDF MTD1N80E Data sheet ( Hoja de datos )
| Número de pieza | MTD1N80E | |
| Descripción | TMOS POWER FET 1.0 AMPERES 800 VOLTS | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD1N80E/D
Designer's
™ Data Sheet
TMOS E-FET .™
Power Field Effect Transistor
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
G
®
D
S
MTD1N80E
Motorola Preferred Device
TMOS POWER FET
1.0 AMPERES
800 VOLTS
RDS(on) = 12 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
800
Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
VDGR
800
Vdc
Gate–to–Source Voltage — Continuous
www.DataSGhaeteet–4tUo–.cSoomurce Voltage — Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
VGS
VGSM
ID
ID
IDM
± 20
± 40
1.0
0.8
3.0
Vdc
Vpk
Adc
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
PD 48 Watts
0.38 W/°C
1.75 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 2.0 Apk, L = 10 mH, RG = 25 Ω)
EAS
20
mJ
Thermal Resistance — Junction to Case
RθJC 2.6 °C/W
Thermal Resistance — Junction to Ambient
RθJA
100
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size
RθJA
71.4
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
© MMoototororloa,laIncT.M19O95S Power MOSFET Transistor Device Data
1
1 page  
12 400
QT
10
VGS 300
8
6
Q1
4
Q2
2
Q3 VDS
0
0246
QT, TOTAL CHARGE (nC)
200
ID = 1 A 100
TJ = 25°C
0
8 10
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
100
VDD = 400 V
ID = 1 A
VGS = 10 V
TJ = 25°C
tf
td(off)
10
tr
MTD1N80E
td(on)
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
www.DataSheet4U.com
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
1.0
VGS = 0 V
TJ = 25°C
0.8
0.6
0.4
0.2
0
0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–Gener-
al Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
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| PDF Descargar | [ Datasheet MTD1N80E.PDF ] | |
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