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AD0804 の電気的特性と機能

AD0804のメーカーはIntersilです、この部品の機能は「(AD0802 - AD0804) 8-Bit Microprocessor-Compatible」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD0804
部品説明 (AD0802 - AD0804) 8-Bit Microprocessor-Compatible
メーカ Intersil
ロゴ Intersil ロゴ 




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AD0804 Datasheet, AD0804 PDF,ピン配置, 機能
August 1997
ADC0802, ADC0803
ADC0804
8-Bit, Microprocessor-
Compatible, A/D Converters
Features
Description
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
• Conversion Time < 100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
• No Zero-Adjust Required
The ADC0802 family are CMOS 8-Bit, successive-approxi-
mation A/D converters which use a modified potentiometric
ladder and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
processor as memory locations or I/O ports, and hence no
interfacing logic is required.
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Ordering Information
PART NUMBER
ADC0802LCN
ADC0802LCD
ADC0802LD
ADC0803LCN
ADC0803LCD
ADC0803LCWM
ADC0803LD
www.DataASDheCe0t840U4.LcoCmN
ADC0804LCD
ADC0804LCWM
ERROR
±1/2 LSB
±3/4 LSB
±1 LSB
±1/2 LSB
±3/4 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
EXTERNAL CONDITIONS
VREF/2 = 2.500VDC (No Adjustments)
VREF/2 Adjusted for Correct Full Scale
Reading
VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC)
PACKAGE
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
PKG. NO
E20.3
F20.3
F20.3
E20.3
F20.3
M20.3
F20.3
E20.3
F20.3
M20.3
Pinout
Typical Application Schematic
ADC0802, ADC0803, ADC0804
(PDIP, CERDIP)
TOP VIEW
CS 1
RD 2
WR 3
CLK IN 4
INTR 5
VIN (+) 6
VIN (-) 7
AGND 8
VREF/2 9
DGND 10
20 V+ OR VREF
19 CLK R
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
ANY
µPROCESSOR
1 CS
2 RD
V+ 20
CLK R 19
+5V 150pF
3 WR CLK IN 4 10K
5 INTR
11 DB7
12 DB6
13 DB5
14 DB4
15 DB3
16 DB2
17 DB1
18 DB0
VIN (+)
VIN (-)
AGND
VREF/2
DGND
6
7
8
9
10
DIFF
INPUTS
VREF/2
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
6-5
File Number 3094.1

1 Page





AD0804 pdf, ピン配列
ADC0802, ADC0803, ADC0804
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Voltage at Any Input . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V+ +0.3V)
Operating Conditions
Temperature Range
ADC0802/03LD. . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
ADC0802/03/04LCD . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
ADC0802/03/04LCN . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
ADC0803/04LCWM . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . 125
N/A
CERDIP Package . . . . . . . . . . . . . . . . . .
80
20
SOIC Package . . . . . . . . . . . . . . . . . . . . . 120
N/A
Maximum Junction Temperature
Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications (Notes 1, 7)
PARAMETER
TEST CONDITIONS
MIN TYP
CONVERTER SPECIFICATIONS V+ = 5V, TA = 25oC and fCLK = 640kHz, Unless Otherwise Specified
Total Unadjusted Error
ADC0802
VREF/2 = 2.500V
--
ADC0803
VREF/2 Adjusted for Correct Full
Scale Reading
-
-
MAX
±1/2
±1/2
ADC0804
VREF/2 = 2.500V
- - ±1
VREF/2 Input Resistance
Input Resistance at Pin 9
1.0 1.3
-
Analog Input Voltage Range
(Note 2)
GND-0.05
- (V+) + 0.05
DC Common-Mode Rejection
Power Supply Sensitivity
Over Analog Input Voltage Range
V+ = 5V ±10% Over Allowed Input
Voltage Range
-
-
±1/16
±1/16
±1/8
±1/8
CONVERTER SPECIFICATIONS V+ = 5V, 0oC to 70oC and fCLK = 640kHz, Unless Otherwise Specified
Total Unadjusted Error
ADC0802
ADC0803
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ADC0804
VREF/2 = 2.500V
VREF/2 Adjusted for Correct Full
Scale Reading
VREF/2 = 2.500V
-
-
-
- ±1/2
- ±1/2
- ±1
VREF/2 Input Resistance
Input Resistance at Pin 9
1.0 1.3
-
Analog Input Voltage Range
(Note 2)
GND-0.05
- (V+) + 0.05
DC Common-Mode Rejection
Power Supply Sensitivity
Over Analog Input Voltage Range
V+ = 5V ±10% Over Allowed Input
Voltage Range
-
-
±1/8
±1/16
±1/4
±1/8
CONVERTER SPECIFICATIONS V+ = 5V, -25oC to 85oC and fCLK = 640kHz, Unless Otherwise Specified
Total Unadjusted Error
ADC0802
ADC0803
VREF/2 = 2.500V
VREF/2 Adjusted for Correct Full
Scale Reading
-
-
- ±3/4
- ±3/4
ADC0804
VREF/2 Input Resistance
Analog Input Voltage Range
DC Common-Mode Rejection
Power Supply Sensitivity
VREF/2 = 2.500V
Input Resistance at Pin 9
(Note 2)
Over Analog Input Voltage Range
V+ = 5V ±10% Over Allowed Input
Voltage Range
-
1.0
GND-0.05
-
-
-
1.3
-
±1/8
±1/16
±1
-
(V+) + 0.05
±1/4
±1/8
UNITS
LSB
LSB
LSB
k
V
LSB
LSB
LSB
LSB
LSB
k
V
LSB
LSB
LSB
LSB
LSB
k
V
LSB
LSB
6-7


3Pages


AD0804 電子部品, 半導体
ADC0802, ADC0803, ADC0804
Typical Performance Curves
1.8
-55oC TO 125oC
1.7
1.6
1.5
1.4
500
400
300
200
1.3
4.50
4.75
5.00
5.25
V+ SUPPLY VOLTAGE (V)
5.50
FIGURE 2. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY
VOLTAGE
100
0
200 400 600 800
LOAD CAPACITANCE (pF)
1000
FIGURE 3. DELAY FROM FALLING EDGE OF RD TO OUTPUT
DATA VALID vs LOAD CAPACITANCE
3.5
3.1 VT(+)
2.7
-55oC TO 125oC
2.3
1.9
VT(-)
1.5
4.50
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4.75
5.00
5.25
V+ SUPPLY VOLTAGE (V)
5.50
FIGURE 4. CLK IN SCHMITT TRIP LEVELS vs SUPPLY VOLTAGE
7
6 V+ = 4.5V
5
4
3
2 V+ = 5V
1
0 V+ = 6V
0
400
800
1200
1600
2000
fCLK (kHz)
FIGURE 6. FULL SCALE ERROR vs fCLK
1000
R = 50K
R = 10K
R = 20K
100
10
100
CLOCK CAPACITOR (pF)
FIGURE 5. fCLK vs CLOCK CAPACITOR
1000
16
VIN(+) = VIN(-) = 0V
14 ASSUMES VOS = 2mV
THIS SHOWS THE NEED
12 FOR A ZERO ADJUSTMENT
IF THE SPAN IS REDUCED
10
8
6
4
2
0
0.01
0.1 1.0
VREF/2 (V)
5
FIGURE 7. EFFECT OF UNADJUSTED OFFSET ERROR
6-10

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