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STA2065 の電気的特性と機能

STA2065のメーカーはSTMicroelectronicsです、この部品の機能は「infotainment application processor」です。


製品の詳細 ( Datasheet PDF )

部品番号 STA2065
部品説明 infotainment application processor
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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STA2065 Datasheet, STA2065 PDF,ピン配置, 機能
www.DataSheet4U.com
STA2065
Cartesio™ family
infotainment application processor with embedded GPS
Data brief
Features
ARM1176 533/624 MHz host processor
– Cache: 32 KB instruction, 32 KB data
– Vector floating point unit
High performance embedded GPS subsystem
– Parallel acquisition engines for 8 GPS
satellites or 4 Galileo satellites
– 32 tracking channels for all satellites in view
– 5 correlators per channel for urban canyon
robustness
– Multibit signal processing hardware
Advanced power management
– Separated power islands for ultra low
power mode
– Dynamic core frequency scaling
– 512-Byte embedded SRAM for back-up
System infrastructure
– LP DDR/DDR2 controller: 16/32bit data
512 MB addressable. (333 MHz DDR2,
200 MHz LPDDR)
– Static memory controller (bootable):
NAND/NOR, SRAM
– One bank of 32 KB embedded SRAM
– 64-channel vector interrupt controller (VIC)
– 2 DMA controllers, 16 physical channels
– 32 DMA request for each controller
– Two external DMA requests are supported
Display and graphics
– Color LCD controller for STN,TFT or HR-
TFT panels with 24-bit parallel RGB
interface
– Integrated touch screen controller and ADC
– 3D advanced graphics acceleration
– Video input port (VIP) interface
– JPEG baseline profile decoder
High throuput interfaces
– 2 ports USB 2.0 OTG with integrated
physical layers
– 3 SD/MMC up to 8 bit data, 2 bootable
TFBGA372+100 (16x16x1.2mm)
Audio interfaces and features
– Four multichannel serial ports (I2S/TDM)
– SPDIF input interface
– C3 hardware reed-solomon decoder
– Sample rate converter
Standard interfaces
– Four 16-bit input capture/output compare
– Pulse width light modulator (PWL)
– Four autobaud UART
– Three I2C multimaster/slave interfaces
– Two synchronous serial port (SSP, SPI)
– Smartcard interface
– Five 32-bit GPIO ports
Two controller area network (CAN) in
automotive version
Programmable voltage IOs: 1.8 V, 2.5 V, 3.3 V
VIOON: 1.8 ±10%V, VDDON: VDD, 1.0 ±10%V
TFBGA 372+100 0.65 mm pitch package,
packing in tray
Ambient temperature range: -40 / +85 °C
Table 1. Device summary
Order code
Qualification
grade
CPU freq.
STA2065N Consumer 533 MHz
STA2065P Consumer 624 MHz
STA2065A Automotive 533 MHz
CAN
No
No
2x
July 2009
Doc ID16050 Rev 1
For further information contact your local STMicroelectronics sales office.
1/20
www.st.com
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STA2065 pdf, ピン配列
www.DataSShTeeAt42U0.6co5m
Contents
2.6.5 SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.6 SPDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.7 AC97 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.8 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Specific functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7.1 GPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7.2 Touchscreen controller/ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7.3 Multisupply IO ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7.4 Driving strength and slew rate programmability . . . . . . . . . . . . . . . . . . . 12
3 System features introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Power region partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Frequency region partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Frequency and power range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 System wakeup and power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 IO groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID16050 Rev 1
3/20


3Pages


STA2065 電子部品, 半導体
www.DataSShyesett4eUm.codmescription
STA2065
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
Real-time clock (RTC)
The RTC provides a one second resolution clock. This keeps time when the system is
inactive and can be used to wake the system up when a programmed ‘alarm’ time is
reached. It has a clock trimming feature to compensate the drift of the 32.768 kHz crystal.
Real-time timer (RTT)
The RTT has the possibility of being clocked off. This reduces the always_on domain
consumption during Deep Sleep. By default the RTT has its clock enabled.
Always_ON supply
The “Always_ON” domain retains its two separate supplies, one for the core logic (VDDON)
and one for the IOs (VIOON).
The VDDON supply is equal to VDD during normal operation but, with the goal of reaching the
lowest consumption possible, can also be configured as low as 1.0 ±10%V when the device
is in deep-sleep.
Enhanced function timer (EFT)
STA2065 features 4 16-bit EFTs. Each of the four EFT timers has a 16-bit free-running
counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse
counter function, and a PWM channel with selectable frequency.
Watchdog timer (WDT)
This OS resource is used to trigger a system reset in the event of software failure.
2.4
2.4.1
Memory interfaces
Flexible static memory controller (FSMC)
The flexible static memory controller (FSMC) supports, with two chip selects:
ROM
Static RAM
NOR type flash memories, not multiplexed
NOR type flash memories, multiplexed
It also supports, with two additional separate chip selects:
NAND type flash memories, SLC small or large page
NAND type flash memories, MLC
For NAND type of memories, the FSMC has been enhanced to implement an error
correction in hardware, based on the Bose-Chaudhuri-Hocquenghem (BCH) code, able to
correct up to 8-bit over 512 bytes+syndrome. The BCH code will calculate, in hardware, the
syndrome only. The actual correction will be implemented through S/W intervention.
6/20 Doc ID16050 Rev 1

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共有リンク

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