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ADV3000 の電気的特性と機能

ADV3000のメーカーはAnalog Devicesです、この部品の機能は「3:1 HDMI/DVI Switch」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADV3000
部品説明 3:1 HDMI/DVI Switch
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADV3000 Datasheet, ADV3000 PDF,ピン配置, 機能
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3:1 HDMI/DVI Switch with Equalization
ADV3000
FEATURES
3 inputs, 1 output HDMI/DVI links
Enables HDMI 1.3-compliant receiver
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables
(20 meters at 2.25 Gbps)
Fully buffered unidirectional inputs/outputs
Globally switchable, 50 Ω on-chip terminations
Pre-emphasized outputs
Low added jitter
Single-supply operation (3.3 V)
4 auxiliary channels per link
Bidirectional unbuffered inputs/outputs
Flexible supply operation (3.3 V to 5 V)
HDCP standard compatible
Allows switching of DDC bus and 2 additional signals
Output disable feature
Reduced power dissipation
Removable output termination
Allows building of larger arrays
Two ADV3000s support HDMI/DVI dual-link
Standards compatible: HDMI receiver, HDCP, DVI
Serial (I2C slave) and parallel control interface
80-lead, 14 mm × 14 mm LQFP, Pb-free package
APPLICATIONS
Multiple input displays
Projectors
A/V receivers
Set-top boxes
Advanced television (HDTV) sets
SET-TOP BOX
HDTV SET
HDMI
RECEIVER
ADV3000
GAME
CONSOLE
DVD PLAYER
NameBrand
Power
DVD 01:18
Figure 1. Typical HDTV Application
FUNCTIONAL BLOCK DIAGRAM
PARALLEL
SERIAL
I2C_SDA
I2C_SCL
I2C_ADDR0
VTTI
22
CONFIG
INTERFACE
RESET
CONTROL
LOGIC
ADV3000
AVCC
DVCC
AMUXVCC
AVEE
DVEE
IP_A[3:0] +
IN_A[3:0]
IP_B[3:0]
+–
IN_B[3:0]
IP_C[3:0] +
IN_C[3:0]
4
4
4
4 EQ
4
4
SWITCH
CORE
PE
4
4
HIGH SPEED BUFFERED
VTTO
+ OP[3:0]
ON[3:0]
VTTI
AUX_A[3:0]
AUX_B[3:0]
AUX_C[3:0]
4
4
4
SWITCH
CORE
4
LOW SPEED UNBUFFERED
BIDIRECTIONAL
Figure 2.
AUX_COM[3:0]
GENERAL DESCRIPTION
The ADV3000 is an HDMI™/DVI switch featuring equalized
TMDS inputs and pre-emphasized TMDS® outputs, ideal for
systems with long cable runs. Outputs can be set to a high
impedance state to reduce the power dissipation and/or to allow
the construction of larger arrays using the wire-OR technique.
The ADV3000 is provided in an 80-lead LQFP, Pb-free, surface-
mount package, specified to operate over the −40°C to +85°C
temperature range.
PRODUCT HIGHLIGHTS
1. Supports data rates up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats, and greater than
UXGA (1600 × 1200) DVI resolutions.
2. Input cable equalizer enables use of long cables at the input
(more than 20 meters of 24 AWG cable at 2.25 Gbps).
3. Auxiliary switch routes a DDC bus and two additional signals
for a single-chip, HDMI 1.3 receive-compliant solution.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.

1 Page





ADV3000 pdf, ピン配列
www.DataSheet4U.com
ADV3000
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
Bit Error Rate (BER)
Added Deterministic Jitter
Added Random Jitter
Differential Intrapair Skew
Differential Interpair Skew1
EQUALIZATION PERFORMANCE
Receiver (Highest Setting)2
Transmitter (Highest Setting)3
INPUT CHARACTERISTICS
Input Voltage Swing
Input Common-Mode Voltage (VICM)
OUTPUT CHARACTERISTICS
High Voltage Level
Low Voltage Level
Rise/Fall Time (20% to 80%)
INPUT TERMINATION
Resistance
AUXILIARY CHANNELS
On Resistance, RAUX
On Capacitance, CAUX
Input/Output Voltage Range
POWER SUPPLY
AVCC
QUIESCENT CURRENT
AVCC
VTTI
VTTO
DVCC
AMUXVCC
POWER DISSIPATION
TIMING CHARACTERISTICS
Switching/Update Delay
RESET Pulse Width
Conditions/Comments
NRZ
PRBS 223 − 1
DR ≤ 2.25 Gbps, PRBS 27 − 1, EQ = 12 dB
At output
At output
Boost frequency = 825 MHz
Boost frequency = 825 MHz
Differential
Single-ended high speed channel
Single-ended high speed channel
Single-ended
Min
2.25
150
AVCC − 800
AVCC − 10
AVCC − 600
75
DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 kHz
DVEE
Operating range
3
Outputs disabled
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
Input termination on4
Output termination on, no pre-emphasis
Output termination on, maximum pre-emphasis
30
52
95
5
35
72
3.2
Outputs disabled
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
High speed switching register: HS_CH
All other configuration registers
115
384
704
50
Typ Max
Unit
10−9
25
1
1
40
Gbps
ps (p-p)
ps (rms)
ps
ps
12 dB
6 dB
1200
AVCC
mV
mV
AVCC + 10 mV
AVCC − 400 mV
135 175
ps
50 Ω
100
8
AMUXVCC
Ω
pF
V
3.3 3.6
V
40 44
60 66
110 122
40 54
40 46
80 90
78
0.01 0.1
mA
mA
mA
mA
mA
mA
mA
mA
271 361
574 671
910 1050
mW
mW
mW
200 ms
1.5 ms
ns
Rev. 0 | Page 3 of 28


3Pages


ADV3000 電子部品, 半導体
ADV3000www.DataSheet4U.com
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVCC 1
IN_B0 2
IP_B0 3
IN_B1 4
IP_B1 5
VTTI 6
IN_B2 7
IP_B2 8
IN_B3 9
IP_B3 10
IN_A0 11
IP_A0 12
IN_A1 13
IP_A1 14
VTTI 15
IN_A2 16
IP_A2 17
IN_A3 18
IP_A3 19
AVEE 20
PIN 1
ADV3000
TOP VIEW
(Not to Scale)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 AVCC
59 IP_C3
58 IN_C3
57 AVEE
56 IP_C2
55 IN_C2
54 VTTI
53 IP_C1
52 IN_C1
51 AVEE
50 IP_C0
49 IN_C0
48 AVCC
47 AVEE
46 VTTI
45 AVCC
44 AVEE
43 I2C_SDA
42 I2C_SCL
41 PP_OCL
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1, 45, 48, 60
AVCC
2 IN_B0
3 IP_B0
4 IN_B1
5 IP_B1
6, 15, 46, 54
VTTI
7 IN_B2
8 IP_B2
9 IN_B3
10 IP_B3
11 IN_A0
12 IP_A0
13 IN_A1
14 IP_A1
16 IN_A2
17 IP_A2
18 IN_A3
19 IP_A3
20, 44, 47, 51, 57
AVEE
21 I2C_ADDR0
22, 76
DVEE
23 PP_CH0
24 PP_CH1
Figure 3. Pin Configuration
Type 1
Power
HS I
HS I
HS I
HS I
Power
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
Power
Control
Power
Control
Control
Description
Positive Analog Supply. 3.3 V nominal.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Negative Analog Supply. 0 V nominal.
I2C Address LSB.
Negative Digital and Auxiliary Multiplexer Power Supply. 0 V nominal.
High Speed Source Selection Parallel Interface LSB.
High Speed Source Selection Parallel Interface MSB.
Rev. 0 | Page 6 of 28

6 Page



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共有リンク

Link :


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