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VSP5000 の電気的特性と機能

VSP5000のメーカーはBurr-Brown Corporationです、この部品の機能は「12-BIT 30 MSPS DUAL CHANNEL CCD SIGNAL FRONT END」です。


製品の詳細 ( Datasheet PDF )

部品番号 VSP5000
部品説明 12-BIT 30 MSPS DUAL CHANNEL CCD SIGNAL FRONT END
メーカ Burr-Brown Corporation
ロゴ Burr-Brown Corporation ロゴ 




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VSP5000 Datasheet, VSP5000 PDF,ピン配置, 機能
www.DataSheet4U.com
VSP5000
SLES057 – DECEMBER 2002
12-BIT 30 MSPS DUAL CHANNEL
CCD SIGNAL FRONT END FOR DIGITAL COPIER
FEATURES
D Dual Channel CCD Signal Processing:
– Correlated Double Sampler (CDS)
– Sample Hold Mode
– Digital Programmable Amplifier
– CCD Offset Correction (OB loop)
D High Performance A/D:
– 12-Bit Resolution
– INL: ±2 LSB
– DNL: ±0.5 LSB
– No Missing Codes
D High-Speed Operation
– Sample Rate: 30 MHz (Minimum)
D 78-dB Signal-To-Noise Ratio (at 0-dB Gain)
D Low Power Consumption:
– Low Voltage: 3 V to 3.6 V
– Low Power: 290 mW (Typ) at 3.3 V
– Standby Mode: 20 mW (Typ)
APPLICATIONS
D Copiers
D Scanners
D Facsimiles
DESCRIPTION
The VSP5000 device is a complete application specific
standard product (ASSP) for charge-coupled device
(CCD) line sensor applications such as copiers, scanners,
and facsimiles. The VSP5000 device provides two
independent channels of processing lines and performs
analog front-end processing and analog-to-digital (A/D)
conversion. Each channel has a correlated double
sampler (CDS)/sample hold (SH) circuit, a 14-bit
analog-to-digital converter (ADC), a digital programmable
gain amplifier (DPGA), and an optical black (OB)
correction loop. Data output is 12 bits in length and the
2-channel A/D data is multiplexed and output.
The VSP5000 is available in a 64-lead LQFP package and
operates from a single 3.3-V supply.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated

1 Page





VSP5000 pdf, ピン配列
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www.DataSheet4U.com
VSP5000
SLES057 DECEMBER 2002
ELECTRICAL CHARACTERISTICS (CONTINUED)
all specifications at TA = 25°C, all power supply voltages = 3.3 V, and conversion rate (fADCCK) = 30 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSP5000
MIN TYP
MAX
ANALOG INPUT (CCDIN)
Input signal level for full-scale output
DPGA gain = 0 dB
1400
Allowable feed-through level
1
Input capacitance
15
Input limit
0.3 3.3
TRANSFER CHARACTERISTICS
DNL Differential nonlinearity
CDS mode, DPGA gain = 0 dB
SH mode, DPGA gain = 0 dB
±0.5 ±1
±0.5 ±1
INL Integral nonlinearity
CDS mode, DPGA gain = 0 dB
SH mode, DPGA gain = 0 dB
±2 ±4
±4
No missing codes
DPGA gain = 0 dB
Assured
Step input settling time
Full-scale step input
1
Overload recovery time
Step input from 2 V to 0 V
2
Data latency
9 (fixed)
Signal-to-noise ratio(1)
DPGA gain = 0 dB
DPGA gain = 24 dB
Channel mismatch
CORRELATED DOUBLE SAMPLER (CDS)
Reference level sample settling time
Within 1 LSB, driver impedance = 50
Data level sample settling time
Within 1 LSB, driver impedance = 50
INPUT CLAMP
Clamp-on resistance
Clamp level
OPTICAL BLACK CLAMP LOOP
CCD offset correction range
DAC resolution
Minimum DAC output current
COB pin
Maximum DAC output current
COB pin
Loop time constant
Slew rate
CCOB = 0.1 µF
CCOB = 0.1 µF, at current DAC full scale
output
Optical black clamp level
Program range
OB clamp code = 0101 0000
REFERENCE
Positive reference voltage
Negative reference voltage
DIGITAL PROGRAMMABLE GAIN AMPLIFIER (DPGA)
Gain program resolution
Gain code = 11 1111 1111 24 dB
Gain
Gain code = 10 0000 0000
Gain code = 00 0100 0000
18 dB
0 dB
Gain code = 00 0000 0000
Gain error
(1) SNR = 20 log (16384 / output rms noise in LSB), input connected to ground through a capacitor.
78
54
8.3
8.3
400
1.5
300
10
±0.15
±153
40.7
1530
0
160
1.85
1.1
10
16
8
1
0
±0.5
±3%
300
510
UNIT
mV
V
pF
V
LSB
LSB
LSB
LSB
pixel
pixels
Clock
Cycles
dB
ns
ns
V
mV
Bits
µA
µA
µs
V/s
LSB
V
V
Bits
V/V
dB
3


3Pages


VSP5000 電子部品, 半導体
VSP5000
wwwS.DLEaSta0S5h7eeDt4EUCE.cMoBmER 2002
www.ti.com
Terminal Functions
TERMINAL
NO. NAME
TYPE(1)
DESCRIPTION
1 B0 (LSB)
DO A/D converter output, bit 0 (LSB)
2 B1
DO A/D converter output, bit 1
3 B2
DO A/D converter output, bit 2
4 B3
DO A/D converter output, bit 3
5 B4
DO A/D converter output, bit 4
6 B5
DO A/D converter output, bit 5
7 CLPOB
DI Optical black clamp pulse
8 SYSCLK
DI System clock input
9 SHD
DI CCD data sampling pulse
10 SHP
DI CCD reference sampling pulse
11 B6
DO A/D converter output, bit 6
12 B7
DO A/D converter output, bit 7
13 B8
DO A/D converter output, bit 8
14 B9
DO A/D converter output, bit 9
15 B10
DO A/D converter output, bit 10
16 B11 (MSB)
DO A/D converter output, bit 11 (MSB)
17 DGND
P Digital ground for digital outputs (B0B11)
18 VDD
19 AGND
P Digital power supply for digital outputs (B0B11)
P Analog ground
20 VCC
21 AGND
P Analog power supply
P Analog ground
22 SDI
DI Serial interface data input
23 SCLK
DI Serial interface data shift clock (triggered at the rising edge)
24 WRT
DI Serial interface data write pulse (triggered at the rising edge)
25 RDO
DO Serial interface register read output
26 AGND
P Analog ground
27 AGND
P Analog ground
28 VCC
29 COB_OD
P Analog power supply
AO Optical black loop output voltage (odd), connect a 0.1-µF capacitor from terminal to ground
30 BYPR_OD
AO Input buffer reference bypass (odd)
31 BYPP_OD
AO CDS positive reference bypass (odd), leave open or bypass to ground through a 0.1-µF capacitor
32 BYPM_OD
AO CDS negative reference bypass (odd), leave open or bypass to ground through a 0.1-µF capacitor
33 BYP_OD
AO CDS common reference bypass (odd), bypass to ground through a 0.1-µF capacitor
34 CCDIN_OD
AI CCD signal input (odd)
35 AGND
P Analog ground
36 VCC
37 REFN_OD
P Analog power supply
AO A/D converter negative reference bypass (odd), bypass to ground through a 0.1-µF capacitor
38 CM_OD
AO A/D converter common reference bypass (odd), bypass to ground through a 0.1-µF capacitor
39 REFP_OD
AO A/D converter positive reference bypass (odd), bypass to ground through a 0.1-µF capacitor
40 VCC
P Analog power supply
41 AGND
P Analog ground
(1) Designators in TYPE: P: power supply and ground, DI: digital input, DO: digital output, AI: analog input, AO: analog output
6

6 Page



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共有リンク

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部品番号部品説明メーカ
VSP5000

12-BIT 30 MSPS DUAL CHANNEL CCD SIGNAL FRONT END

Burr-Brown Corporation
Burr-Brown Corporation
VSP5000

12-Bit 30 MSPS Dual Channel CCD Signal Front End for Digital Copier (Rev. A)

Texas Instruments
Texas Instruments


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