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74HCT08 の電気的特性と機能

74HCT08のメーカーはNXP Semiconductorsです、この部品の機能は「Quad 2-input AND gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HCT08
部品説明 Quad 2-input AND gate
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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74HCT08 Datasheet, 74HCT08 PDF,ピン配置, 機能
74HC08; 74HCT08
Quad 2-input AND gate
Rev. 5 — 30 November 2015
Product data sheet
1. General description
The 74HC08; 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC08: CMOS level
For 74HCT08: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range
74HC08D
40 C to +125 C
74HCT08D
74HC08DB 40 C to +125 C
74HCT08DB
74HC08PW 40 C to +125 C
74HCT08PW
74HC08BQ 40 C to +125 C
74HCT08BQ
Name
SO14
SSOP14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads; body width
3.9 mm
Version
SOT108-1
plastic shrink small outline package; 14 leads; body SOT337-1
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm

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74HCT08 pdf, ピン配列
NXP Semiconductors
74HC08; 74HCT08
Quad 2-input AND gate
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin description
Pin
1, 4, 9, 12
2, 5, 10,13
3, 6, 8, 11
7
14
6. Functional description
Description
data input
data input
data output
ground (0 V)
supply voltage
Table 3.
Input
nA
L
L
H
H
Function table[1]
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
nB
L
H
L
H
Output
nY
L
L
L
H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK input clamping current
IOK output clamping current
IO output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
0.5
[1] -
[1] -
-
+7 V
20 mA
20 mA
25 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
SO14, (T)SSOP14 and DHVQFN14
packages
-
50
65
[2] -
50
-
+150
500
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 15


3Pages


74HCT08 電子部品, 半導体
NXP Semiconductors
74HC08; 74HCT08
Quad 2-input AND gate
Table 7. Dynamic characteristics
GND = 0 V; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
Conditions
Min
CPD power dissipation per package; VI = GND to VCC
capacitance
74HCT02
tpd propagation delay nA, nB to nY; see Figure 6
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
tt
transition time
VCC = 4.5 V; see Figure 6
CPD power dissipation per package;
capacitance
VI = GND to VCC 1.5 V
[3]
[1]
[2]
[3]
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
-
-
-
-
-
25 C
Typ
10
14
11
7
20
40 C to +125 C Unit
Max Max
Max
(85 C) (125 C)
--
- pF
24 30
--
15 19
--
36 ns
- ns
22 ns
- pF
11. Waveforms
9,
Q$Q%LQSXW
*1'
92+
Q<RXWSXW
92/
90
W3+/
9<
W7+/
90
9;
W3/+
W7/+
Fig 6.
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Input to output propagation delays
DDD
Table 8. Measurement points
Type
Input
74HC08
74HCT08
VM
0.5VCC
1.3 V
Output
VM
0.5VCC
1.3 V
VX
0.1VCC
0.1VCC
VY
0.9VCC
0.9VCC
74HC_HCT08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 15

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共有リンク

Link :


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