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PDF ISL12030 Data sheet ( Hoja de datos )
| Número de pieza | ISL12030 | |
| Descripción | Low Power RTC | |
| Fabricantes | Intersil Corporation | |
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ISL12030
®
Real Time Clock with 50/60 Hz Clock and Alarms
Data Sheet
December 14, 2007
FN6617.0
Low Power RTC with 50/60 Cycle AC
Input, Alarms and Daylight Savings
www.Cdaotarshreeect4tui.oconm
The ISL12030 device is a low power real time clock with
50/60 AC input for timing synchronization, clock/calendar
registers, single periodic or polled alarms. There are 128
bytes of user SRAM.
The oscillator uses a 50/60 cycle sine wave input. The real
time clock tracks time with separate registers for hours,
minutes, and seconds. The calendar registers contain the
date, month, year, and day of the week. The calendar is
accurate through year 2100, with automatic leap year
correction and auto daylight savings correction.
Pinout
ISL12030
(8 LD SOIC)
TOP VIEW
NC 1
GND 2
AC 3
NC 4
8 VDD
7 IRQ
6 SCL
5 SDA
Features
• 50/60 Cycle AC as a Primary Clock Input for RTC Timing
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, Seconds and tenths of a
Second
- Day of the Week, Day, Month and Year
• Auto Daylight Saving Time Correction
- Programmable Forward and Backward Dates
• Dual Alarms with Hardware and Register Indicators
- Hardware Single Event or Pulse Interrupt Mode
• 128 Bytes of User SRAM
• I2C Interface
- 400kHz Data Transfer Rate
• Pb-free (RoHS compliant)
Applications
• Utility Meters
• Control Applications
• Vending Machines
• White Goods
• Consumer Electronics
Ordering Information
PART NUMBER
(Note)
ISL12030IBZ*
PART MARKING
12030 IBZ
VDD RANGE
2.7V to 5.5V
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
8 Ld SOIC
PKG DWG #
M8.15
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL12030
I2C Interface Specifications Specifications apply for: VDD = 2.7 to 5.5V, TA = -40°C to +85°C,
unless otherwise stated. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 3) (Note 8) UNITS NOTES
RPU
www.datasheet4u.com
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by
tR and tF.
For Cb = 400pF, max is about
2kΩ.
For Cb = 40pF, max is about
15kΩ
1
kΩ 7
NOTES:
2. IRQ Inactive.
3. Specified at TA =+25°C.
4. FSCL = 400kHz.
5. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
6. Parameter is not 100% tested.
7. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
8. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
5 FN6617.0
December 14, 2007
5 Page 
ISL12030
cleared to “0”, the alarm will operate in standard mode,
where the IRQ pin will be set LOW until both the
ALM0/ALM1 status bits are cleared to “0”.
ALARM 1 (ALE 1)
This bit enables the Alarm1 function. When ALE1 = “1”, a
match of the RTC section with the Alarm1 section will result
www.idsastaesthtienegt4thu.ecoAmLM1 status bit to “1” and the IRQ output LOW.
When set to “0”, the Alarm1 function is disabled.
ALARM 0 (ALE 0)
This bit enables the Alarm0 function. When ALE0 = 1, a
match of the RTC section with the Alarm1 section will result
is setting the ALM0 status bit to “1” and the IRQ output LOW.
When set to “0”, the Alarm0 function is disabled.
AC Register (AC)
Address [13h]
This register sets the parameters for the AC input.
TABLE 4. AC REGISTER
ADDR 7
6 54321
13h AC5060 X
X X X XX
0
X
AC 50/60HZ INPUT SELECT (AC5060)
This bit selects either 50Hz or 60Hz powerline AC clock
input frequency. Setting this bit to “0” selects a 60Hz input
(default). Setting this bit to “1” selects a 50Hz input.
DST Control Registers (DSTCR)
Address [15h to 1Ch]
8 bytes of control registers have been assigned for the
Daylight Savings Time (DST) functions. DST beginning (set
Forward) time is controlled by the registers DstMoFd,
DstDwFd, DstDtFd, and DstHrFd. DST ending time (set
Backward or Reverse) is controlled by DstMoRv, DstDwRv,
DstDtRv and DstHrRv.
Tables 5 and 6 describe the structure and functions of the
DSTCR.
DST FORWARD REGISTERS (15H TO 18H)
DSTE is the DST Enabling Bit located in bit 7 of register 15h
(DstMoFdxx). Set DSTE = 1 will enable the DSTE function.
Upon powering up for the first time, the DSTE bit defaults to
“0”.
DST forward is controlled by the following DST Registers:
DstMoFd sets the Month that DST starts. The default value
for the DST begin month is April (04h).
DstDwFd sets the Week and the Day of the Week that DST
starts. DstDwFdE sets the priority of the Day of the Week
over the Date. For DstDwFdE=1, Day of the week is the
priority. Note that Day of the week counts from 0 to 6, like the
RTC registers. The default for the DST Forward Day of the
Week is Sunday (00h).
WkFd controls the week of the month that the DST starts.
When the day of week option is selected, the WkFd entry set
the week in the month and the DwFd selects the day of the
week. The range for WdFd is 1 to 5 and 7 with 7 being the
last week. Default is 0 (OFF).
DstDtfd controls which Date DST begins. The default value
for DST forward date is on the first date of the month (01h).
DstDtFd is only effective if DwFdE = 0.
DstHrFd controls the hour that DST begins. It includes the
MIL bit, which is in the corresponding RTC register. The RTC
hour and DstHrFd registers need to match formats (Military
or AM/PM) in order for the DST function to work. The default
value for DST hour is 2:00AM (02h). The time is advanced
from 2:00:00AM to 3:00:00AM for this setting.
DST REVERSE REGISTERS (19H TO 1CH)
DST end (reverse) is controlled by the following DST
Registers:
DstMoRv sets the Month that DST ends. The default value
for the DST end month is October (10h).
DstDwRv controls the Week and the Day of the Week that
DST should end. The DwRvE bit sets the priority of the Day of
the Week over the Date. For DwRvE = 1, Day of the week is
the priority. Note that Day of the week counts from 0 to 6, like
the RTC registers. The default for DST DwRv end is Sunday
(00h).
WkRv controls the week of the month that the DST starts.
When the day of week option is selected, the WkRv entry set
the week in the month and the DwRv selects the day of the
week. The range for WdRv is 1 to 5 and 7 with 7 being the
last week. Default is 0 (OFF)
DstDtRv controls which Date DST ends. The default value
for DST Date Reverse is on the first date of the month. The
DstDtRv is only effective if the DwRvE = 0.
DstHrRv controls the hour that DST ends. It includes the MIL
bit, which is in the corresponding RTC register. The RTC
hour and DstHrRv registers need to match formats (Military
or AM/PM) in order for the DST function to work. The default
value sets the DST end at 2:00AM. The time is set back from
2:00:00AM to 1:00:00AM for this setting.
11 FN6617.0
December 14, 2007
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ISL12030.PDF ] | |
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