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PDF VS1011E Data sheet ( Hoja de datos )
| Número de pieza | VS1011E | |
| Descripción | MP3 AUDIO DECODER | |
| Fabricantes | VLSI | |
| Logotipo |  |
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VS1011e
VS1011e - MP3 AUDIO DECODER
Features
• Decodes MPEG 1.0 & 2.0 audio layer
III (MP3: CBR, VBR, ABR); layers I &
II (MP1, MP2) optional; WAV (PCM +
IMA ADPCM)
• 320 kbit/s MP3 with 12.0 MHz external
clock
• Streaming support for all audio formats
• Bass and treble controls
• Operates with single 12..13 MHz or 24..26
MHz external clock
• Internal clock doubler
• Low-power operation
• High-quality stereo DAC with no phase
error between channels
• Stereo earphone driver capable of driv-
ing a 30Ω load
• Separate 2.5 .. 3.6 V operating volt-
ages for analog and digital
• Serial control and data interfaces
• Can be used as a slave co-processor
• 5.5 KiB On-chip RAM for user code /
data
• SPI boot for standalone applications
• New functions may be added with soft-
ware and 4 GPIO pins
• Lead-free and RoHS-compliant packages
LPQFP-48, BGA-49, and SOIC-28
Description
VS1011e is a single-chip MPEG audio (MP3)
decoder IC. The circuit contains a high-performance,
low-power DSP processor core VS_DSP4, work-
ing memory, 5 KiB instruction RAM and 0.5
KiB data RAM for user applications, serial con-
trol and input data interfaces, 4 general pur-
pose I/O pins, as well as a high-quality variable-
sample-rate stereo DAC, followed by an ear-
phone amplifier and a common buffer.
VS1011e receives its input bitstream through
a serial input bus, which it listens to as a
system slave. The input stream is decoded
and passed through a digital volume control
to an 18-bit oversampling, multi-bit, sigma-
delta DAC. The decoding is controlled via a
serial control bus. In addition to basic decod-
ing, it is possible to add application specific
features, like DSP effects, to the user RAM
memory.
VS1011e can boot directly from SPI EEPROM
to run standalone applications without a sep-
arate microcontroller.
VS1011
GPIO
GPIO
4
Stereo
DAC
DREQ
SO
SI
SCLK
XCS
XDCS
Serial
Data/
Control
Interface
VSDSP4
Instruction
RAM
Instruction
ROM
Stereo Ear−
phone Driver
X ROM
audio
L
R
output
X RAM
Y ROM
Y RAM
Version: 1.22, 2014-12-19
1
1 page  
VS1011e
LIST OF FIGURES
List of Figures
1 Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Package Outline, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Pin Configuration, BGA-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Pin Configuration, SOIC-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Typical Connection Diagram Using LQFP-48. . . . . . . . . . . . . . . . . . . . . 15
6 SDI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10 SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11 SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12 Two SCI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13 Two SDI Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
14 Two SDI Bytes Separated By an SCI Operation. . . . . . . . . . . . . . . . . . . . 23
15 Data Flow of VS1011e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16 User’s Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Version: 1.22, 2014-12-19
5
5 Page 
LQFP-48 Package Outline
VS1011e
5 PACKAGES AND PIN DESCRIPTIONS
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Figure 2: Package Outline, LQFP-48.
Version: 1.22, 2014-12-19
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11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VS1011E.PDF ] | |
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