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PDF V54C3128164VAT Data sheet ( Hoja de datos )
| Número de pieza | V54C3128164VAT | |
| Descripción | High Performance SDRAM | |
| Fabricantes | Mosel Vitelic | |
| Logotipo |  |
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MOSEL VITELIC
V54C3128164VAT
w w w . D a t a S h e e t 4 U .HcIGo Hm PERFORMANCE 166/143/133/125MHz
3.3 VOLT 8M X 16 SYNCHRONOUS DRAM
4 BANKS X 2Mbit X 16
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
Clock Access Time (tAC1) CAS Latency = 1
6
166 MHz
6
5.4 ns
5.4 ns
10.5 ns
7
143 MHz
7 ns
5.4 ns
5.5 ns
10.5 ns
75
133 MHz
7.5 ns
5.4 ns
6 ns
10.5 ns
8PC
125 MHz
8 ns
6 ns
6 ns
10.5 ns
Features
s 4 banks x 2Mbit x 16 organization
s High speed data transfer rates up to 166 MHz
s Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s Single Pulsed RAS Interface
s Data Mask for Read/Write Control
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency:1, 2, 3
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
s Multiple Burst Read with Single Write Operation
s Automatic and Controlled Precharge Command
s Random Column Address every CLK (1-N Rule)
s Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 54 Pin 400 mil TSOP-II
s LVTTL Interface
s Single +3.3 V ±0.3 V Power Supply
Description
The V54C3128164VAT is a four bank Synchro-
nous DRAM organized as 4 banks x 2Mbit x 16. The
V54C3128164VAT achieves high speed data trans-
fer rates up to 166 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T
•
6
•
Access Time (ns)
7PC 7
••
8PC
•
Power
Std. L
••
Temperature
Mark
Blank
V54C3128164VAT Rev. 1.9 August 2001
1
1 page  
MOSEL VITELIC
V54C3128164VAT
www.DataSheet4U.com
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Operation
Row Activate
Read
Read w/Autoprecharge
Write
Write with Autoprecharge
Row Precharge
Precharge All
Mode Register Set
No Operation
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Power Down Entry
Power Down Exit
Data Write/Output Enable
Data Write/Output Disable
Device CKE CKE
A0-9,
BS0
State n-1 n CS RAS CAS WE DQM A11 A10 BS1
Idle3 H X L L H H X V V V
Active3
H
X
LHLHXVL
V
Active3
H
X
L
H
L
H
X
V
H
V
Active3
H
X
LHL
L
XVL
V
Active3
H
X
L
H
L
L
X
V
H
V
Any H X L L H L X X L V
Any H X L L H L X X H X
Idle H X L L L L X V V V
Any
HX
L HHH X
XX
X
Any H X H X X X X X X X
Idle H H L L L H X X X X
Idle H L L L L H X X X X
Idle H X X X
(Self Refr.) L
H
XXX X
LHHX
Idle H X X X
Active4
H
L
XXX X
LHHX
Any H X X X
(Power
L
H
XXX X
Down)
LHHL
Active H X X X X X L X X X
Active H X X X X X H X X X
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Power Down Mode can not entry in the burst cycle.
V54C3128164VAT Rev. 1.9 August 2001
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MOSEL VITELIC
V54C3128164VAT
wwwA.DCatCaShhaeerta4cUt.ceormistics 1,2, 3
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Limit Values
-6 -7PC -7 -8PC
# Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Clock and Clock Enable
1 tCK Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
6–7–7– 8 –
7.5 – 7.5 – 10 – 10 –
10.5 – 10.5 – 10.5 – 10.5 –
s
ns
ns
ns
2 tCK Clock Frequency
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
– 166 – 143 – 143 – 125 MHz
– 133 – 133 – 100 – 100 MHz
– 83 – 83 – 83 – 83 MHz
3 tAC Access Time from Clock
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
– 5.4 – 5.4 – 5.4 – 6 ns
_ 5.4 _ 5.4 _ 6 _ 6 ns
_ 10.5 _ 10.5 _ 10.5 _ 10.5 ns
2, 4
4 tCH Clock High Pulse Width
5 tCL Clock Low Pulse Width
6 tT Transition Tim
Setup and Hold Times
2.5 – 2.5 – 2.5 – 3
2.5 – 2.5 – 2.5 – 3
0.3 1.2 0.3 1.2 0.3 1.2 0.5
–
–
10
ns
ns
ns
7 tIS Input Setup Time
8 tIH Input Hold Time
9 tCKS Input Setup Time
10 tCKH CKE Hold Time
11 tRSC Mode Register Set-up Time
12 tSB Power Down Mode Entry Time
Common Parameters
1.5 – 1.5 – 1.5 – 2 –
0.8 – 0.8 – 0.8 – 1 –
1.5 – 1.5 – 1.5 – 2 –
0.8 – 0.8 – 0.8 – 1 –
12 – 14 – 14 – 16 –
060707 0 8
ns
ns
ns
ns
ns
ns
5
5
5
5
13 tRCD Row to Column Delay Time
14 tRP Row Precharge Time
15 tRAS Row Active Time
16 tRC Row Cycle Time
17 tRRD Activate(a) to Activate(b) Command Period
18 tCCD CAS(a) to CAS(b) Command Period
Refresh Cycle
12 – 15 – 15 – 20 – ns
15 – 15 – 15 – 20 – ns
40 100K 42 100K 42 100K 45 100k ns
60 – 60 – 60 – 60 – ns
12 – 14 – 14 – 16 – ns
1 – 1 – 1 – 1 – CLK
6
6
6
6
6
19 tREF Refresh Period (4096 cycles)
20 tSREX Self Refresh Exit Time
— 64 — 64 — 64 — 64 ms
1 — 1 — 1 — 1 — CLK
V54C3128164VAT Rev. 1.9 August 2001
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet V54C3128164VAT.PDF ] | |
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