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PDF 74V2T02 Data sheet ( Hoja de datos )
| Número de pieza | 74V2T02 | |
| Descripción | DUAL 2-INPUT NOR GATE | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74V2T02
DUAL 2-INPUT NOR GATE
s HIGH SPEED: tPD = 5.1ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
www.DataSheet4U.csomICCOC M=P1AµTAI(BMLAEXW.)IaTtHTATT=L2O5°UCTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8mA (MIN) at VCC = 4.5V
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V2T02 is an advanced high-speed CMOS
DUAL 2-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
SOT23-8L
ORDER CODES
PACKAGE
SOT23-8L
T&R
74V2T02STR
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 2003
1/7
1 page  
DIM.
A
www.DataSheet4U.com
A1
A2
b
C
D
E
E1
e
e1
L
SOT23-8L MECHANICAL DATA
MIN.
0.90
0.00
0.90
0.22
0.09
2.80
2.60
1.50
0
0.35
mm.
TYP
.65
1.95
MAX.
1.45
0.15
1.30
0.38
0.20
3.00
3.00
1.75
MIN.
35.4
0.0
35.4
8.6
3.5
110.2
102.3
59.0
0.55 13.7
mils
TYP.
25.6
76.7
74V2T02
MAX.
57.1
5.9
51.2
14.9
7.8
118.1
118.1
68.8
21.6
5/7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74V2T02.PDF ] | |
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