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PDF S1R72900F00A Data sheet ( Hoja de datos )
| Número de pieza | S1R72900F00A | |
| Descripción | IEEE1394 Controller | |
| Fabricantes | Epson | |
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MF1449-01
IEEE1394 Controller
S1R75289010F00A
Technical Manual
1 page  
1. DESCRIPTION
The SIR72900F00A is a physical layer IC compliant
with the IEEE 1394-1995 and IEEE 1394a-2000
standards.
With the two 1394 ports, the SIR72900F00A supports
transmission speeds of 400/200/100 Mbit/sec. The
product incorporates a 400-MHz PLL, reference voltage
generating circuit, high-speed transceiver, LINK layer
interface, and a state machine circuit for bus initialization
and arbitration.
www.DataSheet4U.com
S1R72900F00A
2. FEATURES
• Complies with the IEEE 1394-1995 and IEEE 1394a-
2000 standards.
• Supports transmission speeds of S400 (393.216 Mbit/
sec), S200 (196.608 Mbit/sec), and S100 (98.304
Mbit/sec).
• Incorporates a 400-MHz PLL for transmission at
S400/S200/S100 and 50-MHz SCLK output.
• Offers independent TpBias output for each port.
• Supports the Cable Power Status function that detects
a cable power drop.
• Supports DC and AC connections of the PHY/LINK
interface.
• Built-in oscillating circuit
• High-accuracy, low-amplitude differential high-speed
transceiver
• Bus initialization, arbitration, port connection, and
control state machine circuits
• PHY/LINK interface circuit
• High-speed DS encoder
• Supports the short bus reset function at detection of
LINK layer IC power-off.
• Single 3.3-V power supply
• 64-Pin Plastic QFP
• Designed with the low-power CMOS technology.
* This product is not radioresistant.
Rev. 1.0
EPSON
1
5 Page 
S1R72900F00A
6. PIN DESCRIPTION
Pin name
AVDD
AVSS
PVDD
PVSS
VDD
VSS
OSCVDD
OSCVSS
www.DataSheet4U.coTmPA0_P
TPA0_N
TPB0_P
TPB0_N
TPBIAS0
TPA1_P
TPA1_N
TPB1_P
TPB1_N
TPBIAS1
R1, R0
PD
BCLKON
LREQ
CTL0, CTL1
D0 to D7
SCLK
LPS
PS2
PS1
PS0
DIRECT
Function
Pin No.
Analog circuit power supply pin
30,31,42,51,52
Analog circuit ground pin
32,33,39,48,49,50
PLL circuit power supply pin
56
PLL circuit ground pin
57
Digital circuit power supply pin
16,25,26,62
Digital circuit ground pin
17,18,63,64
Oscillating circuit power supply pin
61
Oscillating circuit ground pin
58
Port 0, TPA+ I/O signal
37
Port 0, TPA– I/O signal
36
Port 0, TPB+ I/O signal
35
Port 0, TPB– I/O signal
34
Port 0, TP bias voltage supply pin
38
Port 1, TPA+ I/O signal
46
Port 1, TPA– I/O signal
45
Port 1, TPB+ I/O signal
44
Port 1, TPB– I/O signal
43
Port 1, TP bias voltage supply pin
47
Connect 6.0kΩ(1.0%) between the
external reference resistor connecting
41,40
pins R1 and R0.
Power down input pin
Connect this pin to VSS during normal
14
operation.
Bus Manager Contender/Link-On pin
The status of this pin determines whether
the bus manager function is used at the
19
time of hard reset. See 7.4.3.
Request signal from the Link layer
controller IC
1
PHY/LINK interface bidirectional control signal
4,5
PHY/LINK interface bidirectional data signal
6,7,8,9,
10,11,12,13
49.152 MHz system clock to the Link
layer controller IC
2
Link power status pin.
A signal used to monitor whether the Link
15
layer controller IC is active.
Power status pin
These pins configure the POWER
CLASS bit of the Self-ID packet. PS0,
20,21,22
PS1, and PS2 are respectively bits 21,
22, 23 of the Self-ID packet.
Configured according to the isolation
barrier configuration between PHY and
LINK.
23
Connect this pin to VDD for DC or single
capacitor AC connection.
Pin typ.
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Differential
Differential
Differential
Differential
Supply
Differential
Differential
Differential
Differential
Supply
Analog
Hysteresis
CMOS
Hysteresis
Hysteresis
Hysteresis
Hysteresis
CMOS
CMOS
I/O
–
–
–
–
–
–
–
–
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
O
O
I
I/O
I
I/O
I/O
O
I
I
I
Rev. 1.0
EPSON
7
11 Page | ||
| Páginas | Total 57 Páginas | |
| PDF Descargar | [ Datasheet S1R72900F00A.PDF ] | |
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