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PDF S1R72801F00A Data sheet ( Hoja de datos )
| Número de pieza | S1R72801F00A | |
| Descripción | IEEE1394 Controller | |
| Fabricantes | Epson | |
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MF1385-04
IEEE1394 Controller
S1R72801F00A
Technical Manual
1 page  
1. DESCRIPTION
The S1R72801F00A is a LINK/Transaction controller
based on the IEEE Std. 1394-1955, P1394a Draft 2.0. It
integrates a built-in CPU and Flash ROM, and also
integrates a part of transaction functions into hardware.
If you set a PageTable address and its size, it can
automatically fetch subsequent PageTables and transmit
data. It can offer a 1394 interface optimum to computer
peripherals in combination with the Cable PHY
Transceiver Arbiter based on the above standard.
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S1R72801F00A
2. FEATURES
q LINK/Transaction Controller
LINK Layer
Ready for all two-way data transfer in Asynchronous
and Isochronous modes.
The built-in SRAM realized stable two-way data
transfer up to max. payload of 100Mbps, 200Mbps,
and 400Mbps.
Can automatically detect the Isochronous Resource
Manager by hardware.
Transaction Layer
Integrates a part of transaction functions into hardware
to prevent deterioration of actual data transmission
rate due to the overhead of firmware (assure a special
area).
A header area is distinguished from a data area to
simplify communications with a higher rank layer.
Furthermore, it segments a data area to a stream area
and ORB area.
Adopts a ring buffer to the receive header area,
receive data area (receive stream area, receive ORB
area) and transmit data area (transmit stream area).
Can arbitrarily set the size of each area.
Automatically controls the Busy when hardware
receives data.
q SBP-2 Support
Can set an PageTable address and its size for the
SBP-2 to automatically perform subsequent Page
Table fetches and data transfers.
q PHY/LINK Interface
Ready for the P1394a.
Ready for the data transfer rate of 100/200/400Mbps.
Ready for isolation (bus holder integrated)
q IDE Interface
Ready for the PIO mode 0/1/2/3/4, multi-word DMA
mode 0/1/2, Ultra-DMA mode 0/1/2.
Usable as a general port interface as well.
EPSON
1
5 Page 
Pin Name PIN I/O Reset
Pin Function
IDE Interface (HVDD)
HDA2
61 Otr Hi-Z (MSB)
HDA1
64 Otr Hi-Z IDE Address Signal
HDA0
62 Otr Hi-Z (LSB)
XHCS1
59 Otr Hi-Z IDE Chip Select Signal
XHCS0
60 Otr Hi-Z IDE Chip Select Signal
XHDASP 56 I – IDE DASP Signal
XHRST
90 Otr Hi-Z IDE Reset Signal
C33 External Interface (HVDD)
AD23
54 O Lo (MSB)
www.DataSheet4UA.cDom22
53 O Lo
AD21
52 O Lo
AD20
51 O Lo
AD19
50 O Lo
AD18
49 O Lo
AD17
44 O Lo
AD16
43 O Lo
AD15
42 O Lo CPU Address Bus
AD14
41 O Lo
AD13
40 O Lo
AD12
39 O Lo
AD11
38 O Lo
AD10
36 O Lo
AD9 35 O Lo
AD8 34 O Lo
AD7 33 O Lo
AD6 32 O Lo
AD5 31 O Lo
AD4 30 O Lo
AD3 28 O Lo
AD2 27 O Lo
AD1 26 O Lo
AD0
25 O Lo (LSB)
DT15
20 B Hi-Z (MSB)
DT14
19 B Hi-Z
DT13
18 B Hi-Z
DT12
17 B Hi-Z
DT11
16 B Hi-Z
DT10
15 B Hi-Z
DT9 14 B Hi-Z
DT8 12 B Hi-Z CPU Data Buss
DT7 11 B Hi-Z
DT6 10 B Hi-Z
DT5 9 B Hi-Z
DT4 8 B Hi-Z
DT3 7 B Hi-Z
DT2 6 B Hi-Z
DT1 4 B Hi-Z
DT0 3 B Hi-Z (LSB)
S1R72801F00A
Remarks
Drive Ability 3mA
Drive Ability 6mA
EPSON
7
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S1R72801F00A.PDF ] | |
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