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PDF SFP840 Data sheet ( Hoja de datos )
| Número de pieza | SFP840 | |
| Descripción | N-Channel MOSFET | |
| Fabricantes | SemiWell Semiconductor | |
| Logotipo |  |
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SemiWell Semiconductor
SFP840
Features
■ High ruggedness
■ RDS(on) (Max 0.85 Ω )@VGS=10V
www.DataSheet4U.com ■ Gate Charge (Typical 48nC)
■ Improved dv/dt Capability, High ruggedness
■ 100% Avalanche Tested
■ Maximum Junction Temperature Range (150°C)
General Description
This Power MOSFET is produced using SemiWell’s advanced
planar stripe, DMOS technology. This latest technology has been
especially designed to minimize on-state resistance, have a high
rugged avalanche characteristics. This devices is specially well
suited for half bridge and full bridge resonant topolgy like a
electronic lamp ballast.
N-Channel MOSFET
Symbol
1. Gate {
{ 2. Drain
●
◀▲
●
●
{ 3. Source
TO-220
123
Absolute Maximum Ratings
Symbol
VDSS
ID
IDM
VGS
EAS
EAR
dv/dt
PD
TSTG, TJ
TL
Parameter
Drain to Source Voltage
Continuous Drain Current(@TC = 25°C)
Continuous Drain Current(@TC = 100°C)
Drain Current Pulsed
Gate to Source Voltage
Single Pulsed Avalanche Energy
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation(@TC = 25 °C)
Derating Factor above 25 °C
Operating Junction Temperature & Storage Temperature
Maximum Lead Temperature for soldering purpose,
1/8 from Case for 5 seconds.
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case to Sink
Thermal Resistance, Junction-to-Ambient
Min.
-
-
-
(Note 1)
(Note 2)
(Note 1)
(Note 3)
Value
500
8
5.1
32
±30
660
12.5
5
125
1.0
- 55 ~ 150
300
Value
Typ.
-
0.5
-
Max.
1
-
62
May, 2003. Rev. 0.
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
Units
V
A
A
A
V
mJ
mJ
V/ns
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
1/7
1 page  
SFP840
Fig. 12. Gate Charge Test Circuit & Waveforms
www.DataSheet4U.com
Same Type
50KΩ
as DUT
12V 200nF
300nF
VGS
10V
VGS
VDS
Qgs
DUT
1mA
Fig 13. Switching Time Test Circuit & Waveforms
Qg
Qgd
Charge
VDS
10V
Pulse
Generator
RG
RL
VDD
( 0.5 rated VDS )
DUT
VDS
90%
Vin 10%
td(on)
tr
t on
td(off)
tf
t off
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
10V
VDS
ID
RG
L
VDD
DUT
EAS = --21--
LL IAS2
------B--V--D--S-S-------
BVDSS -- VDD
BVDSS
IAS
ID (t)
VDD
VDS (t)
t p Time
5/7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SFP840.PDF ] | |
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