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S29NS128PのメーカーはSPANSIONです、この部品の機能は「MirrorBit Flash Family」です。 |
部品番号 | S29NS128P |
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部品説明 | MirrorBit Flash Family | ||
メーカ | SPANSION | ||
ロゴ | |||
このページの下部にプレビューとS29NS128Pダウンロード(pdfファイル)リンクがあります。 Total 30 pages
S29NS-P MirrorBitTM Flash Family
www.DataSheetS4U2.c9omNS512P S29NS256P S29NS128P
512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V Burst Simultaneous
Read/Write, Multiplexed MirrorBit Flash Memory
Data Sheet (Advance Information)
S29NS-P MirrorBitTM Flash Family Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S29NS-P_00
Revision A Amendment 1
Issue Date February 20, 2007
1 Page S29NS-P MirrorBitTM Flash Family
S29NS512P S29NS256P S29NS128P
512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V Burst Simultaneous
Read/Write, Multiplexed MirrorBit Flash Memory
Data Sheet (Advance Information)
Features
Single 1.8 V read/program/erase (1.70–1.95 V)
90 nm MirrorBit Technology
www.DataSheet4UM.cuolmtiplexed Data and Address for reduced I/O count
Simultaneous Read/Write operation
Full/Half drive output slew rate control
32-word Write Buffer
Sixteen-bank architecture consisting of
64/32/16 MB for NS512/256/128P, respectively
Four 32 KB sectors at the top of memory array (NS256/128P)
512 128KB sectors (NS512P), 255/127 128KB sectors (NS256/
128P)
Programmable linear (8/16/32) with or without wrap around
and continuous burst read modes
Secured Silicon Sector region consisting of 128 words each
for factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector (typical)
RDY output indicates data available to system
Command set compatible with JEDEC (42.4) standard
Hardware (WP#) protection of highest two sectors
Top Boot sector configuration (NS256/128P)
Handshaking by monitoring RDY
Offered Packages
– NS512P: 64-ball FBGA (8 mm x 9.2 mm)
– NS256P/NS128P: 44-ball FBGA (6.2 mm x 7.7 mm)
Low VCC write inhibit
Persistent and Password methods of Advanced Sector
Protection
Write operation status bits indicate program and erase
operation completion
Suspend and Resume commands for Program and Erase
operations
Unlock Bypass program command to reduce programming
time
Synchronous or Asynchronous program operation,
independent of burst control register settings
VPP input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch. Latency, ns (tIACC)
Max. Synch. Burst Access, ns (tBACC)
Max. Asynch. Access Time, ns (tACC)
Max OE# Access Time, ns (tOE)
108
80
7.0
80
7.0
Current Consumption (typical values)
Continuous Burst Read @ 108 MHz
Simultaneous Operation 108 MHz
Program
Standby Mode
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (VCC) Per Word
Effective Write Buffer Programming (VPP) Per Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
42 mA
60 mA
30 mA
20 µA
30 µs
6 µs
4 µs
350 ms
600 ms
General Description
The Spansion S29NS512/256/128P are MirrorBit Flash products fabricated on 90 nm process technology. These burst mode
Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using
multiplexed data and address pins. These products can operate up to 108 MHz and use a single VCC of 1.7 V to 1.95 V that
makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered
power consumption.
Publication Number S29NS-P_00
Revision A Amendment 1
Issue Date February 20, 2007
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
3Pages Data Sheet (Advance Information)
Tables
www.DataSheet4U.com
6
Table 2.1
Table 5.1
Table 5.2
Table 5.3
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 6.8
Table 6.9
Table 6.10
Table 6.11
Table 6.12
Table 6.13
Table 6.14
Table 6.15
Table 6.16
Table 6.17
Table 6.18
Table 6.19
Table 6.20
Table 6.21
Table 6.22
Table 6.23
Table 6.24
Table 6.25
Table 6.26
Table 6.27
Table 6.28
Table 6.29
Table 7.1
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10
Table 10.11
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
S29NS512P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
S29NS256P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
S29NS128P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Address Latency for 2 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Programmable Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Secured Silicon SectorSecure Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Secured Silicon Sector Entry (LLD Function = lld_SecSiSectorEntryCmd) . . . . . . . . . . . . . .62
Secured Silicon Sector Program (LLD Function = lld_ProgramCmd) . . . . . . . . . . . . . . . . . . .62
Secured Silicon Sector Exit (LLD Function = lld_SecSiSectorExitCmd) . . . . . . . . . . . . . . . . .63
DC Characteristics—CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
VCC Power-Up with No Ramp Rate Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Synchronous Wait State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Asynchronous Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Example of Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
S29NS-P MirrorBitTM Flash Family
S29NS-P_00_A1 February 20, 2007
6 Page | |||
ページ | 合計 : 30 ページ | ||
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PDF ダウンロード | [ S29NS128P データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
S29NS128J | Burst Mode Flash Memories | SPANSION |
S29NS128N | Burst Mode Flash Memory | SPANSION |
S29NS128P | MirrorBit Flash Family | SPANSION |