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PDF 89LP4052 Data sheet ( Hoja de datos )
| Número de pieza | 89LP4052 | |
| Descripción | AT89LP4052 | |
| Fabricantes | ATMEL Corporation | |
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Features
• Compatible with MCS®51 Products
• 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions
• Single Clock Cycle per Byte Fetch
• 2/4K Bytes of In-System Programmable (ISP) Flash Memory
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 32-byte User Signature Array
• 2.4V to 5.5V VCC Operating Range
• Fully Static Operation: 0 Hz to 20 MHz
• 2-level Program Memory Lock
• 256 x 8 Internal RAM
www.Data•ShHeeatr4dUw.caorme Multiplier
• 15 Programmable I/O Lines
• Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
• Enhanced UART with Automatic Address Recognition and Framing Error Detection
• Enhanced SPI with Double-buffered Send/Receive
• Programmable Watchdog Timer with Software Reset
• 4-level Interrupt Priority
• Analog Comparator with Selectable Interrupt and Debouncing
• Two 16-bit Enhanced Timer/Counters with 8-bit PWM
• Brown-out Detector and Power-off Flag
• Internal Power-on Reset
• Low Power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
8-bit
Microcontroller
with 2/4-Kbyte
Flash
AT89LP2052
AT89LP4052
1. Description
The AT89LP2052/LP4052 is a low-power, high-performance CMOS 8-bit microcon-
troller with 2/4K bytes of In-System Programmable Flash memory. The device is
manufactured using Atmel's high-density nonvolatile memory technology and is com-
patible with the industry-standard MCS-51 instruction set. The AT89LP2052/LP4052
is built around an enhanced CPU core that can fetch a single byte from memory every
clock cycle. In the classic 8051 architecture, each fetch required 6 clock cycles, forc-
ing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP2052/LP4052
CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more through-
put than the standard 8051. Seventy percent of instructions need only as many clock
cycles as they have bytes to execute, and most of the remaining instructions require
only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput
whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consump-
tion. Conversely, at the same throughput as the classic 8051, the new CPU core runs
at a much lower speed and thereby greatly reduces power consumption.
3547F–MICRO–6/06
1 page  
Figure 5-1. Program Memory Map
AT89LP2052/LP4052
0FFF
07FF
Program Memory
AT89LP2052
Program Memory
AT89LP4052
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0000
0000
5.2 Data Memory
The AT89LP2052/LP4052 contains 256 bytes of general SRAM data memory plus 128 bytes of
I/O memory. The lower 128 bytes of data memory may be accessed through both direct and
indirect addressing. The upper 128 bytes of data memory and the 128 bytes of I/O memory
share the same address space (see Figure 5-2). The upper 128 bytes of data memory may only
be accessed using indirect addressing. The I/O memory can only be accessed through direct
addressing and contains the Special Function Registers (SFRs). The lowest 32 bytes of data
memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits (PSW.3 and
PSW.4) select which register bank is in use. Instructions using register addressing will only
access the currently specified bank. The AT89LP2052/LP4052 does not support external data
memory.
Figure 5-2. Data Memory Map
FFH
Upper
128
80H
7FH
Lower
128
Accessible
By Indirect
Addressing
Only
Accessible
By Direct and
Indirect
Addressing
0
Accessible
By Direct
Addressing
FFH
80H
Special
Function
Registers
Ports
Status and
Control Bits
Timers
Registers
Stack Pointer
Accumulator
(Etc.)
3547F–MICRO–6/06
5
5 Page 
AT89LP2052/LP4052
11. Reset
During reset, all I/O Registers are set to their initial values, the port pins are tri-stated, and the
program starts execution from the Reset Vector, 0000H. The AT89LP2052/LP4052 has four
sources of reset: power-on reset, brown-out reset, external reset, and watchdog reset.
11.1 Power-on Reset
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A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level is
nominally 1.4V. The POR is activated whenever VCC is below the detection level. The POR cir-
cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices
without a brown-out detector. The POR circuit ensures that the device is reset from power-on.
When VCC reaches the Power-on Reset threshold voltage, the POR delay counter determines
how long the device is kept in POR after VCC rise. The POR signal is activated again, without
any delay, when VCC falls below the POR threshold level. A Power-on Reset (i.e. a cold reset)
will set the POF flag in PCON.
11.2
Brown-out Reset
The AT89LP2052/LP4052 has an on-chip Brown-out Detection (BOD) circuit for monitoring the
VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD is
nominally 2.2V. The purpose of the BOD is to ensure that if VCC fails or dips while executing at
speed, the system will gracefully enter reset without the possibility of errors induced by incorrect
execution. When VCC decreases to a value below the trigger level, the Brown-out Reset is imme-
diately activated. When VCC increases above the trigger level, the BOD delay counter starts the
MCU after the time-out period has expired.
11.3
External Reset
The RST pin functions as an active-high reset input. The pin must be held high for at least two
clock cycles to trigger the internal reset. RST also serves as the In-System Programming (ISP)
enable. ISP is enabled when the external reset pin is held high and the ISP Enable fuse is
enabled.
11.4
Watchdog Reset
When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles.
Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the
watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times
out. A Watchdog reset will occur only if the Watchdog has been enabled. The Watchdog is dis-
abled by default after any reset and must always be re-enabled if needed.
12. Power Saving Modes
The AT89LP2052/LP4052 supports two different power-reducing modes: Idle and Power-down.
These modes are accessed through the PCON register.
3547F–MICRO–6/06
11
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| PDF Descargar | [ Datasheet 89LP4052.PDF ] | |
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