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V54C365164VL の電気的特性と機能

V54C365164VLのメーカーはMosel Vitelicです、この部品の機能は「HIGH PERFORMANCE 225/200/166/143 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16」です。


製品の詳細 ( Datasheet PDF )

部品番号 V54C365164VL
部品説明 HIGH PERFORMANCE 225/200/166/143 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16
メーカ Mosel Vitelic
ロゴ Mosel Vitelic ロゴ 




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V54C365164VL Datasheet, V54C365164VL PDF,ピン配置, 機能
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MOSEL VITELIC
V54C365164VD(L)
HIGH PERFORMANCE 225/200/166/143 MHz
3.3 VOLT 4M X 16 SYNCHRONOUS DRAM
4 BANKS X 1Mbit X 16
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
Clock Access Time (tAC1) CAS Latency = 1
45
225 MHz
4.5 ns
4.5 ns
4.5 ns
12 ns
5
200 MHz
5 ns
5 ns
5 ns
12 ns
6
166 MHz
6 ns
5.4 ns
5.5 ns
12 ns
7
143 MHz
7 ns
5.4 ns
5.5 ns
12 ns
Features
s 4 banks x 1Mbit x 16 organization
s High speed data transfer rates up to 225 MHz
s Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s Single Pulsed RAS Interface
s Data Mask for byte Control
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 1, 2, 3
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
s Multiple Burst Read with Single Write Operation
s Automatic and Controlled Precharge Command
s Random Column Address every CLK (1-N Rule)
s Suspend Mode and Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 54 Pin 400 mil TSOP-II
s LVTTL Interface
s Single +3.3 V ±0.3 V Power Supply
Description
The V54C365164VD(L) is a four bank Synchro-
nous DRAM organized as 4 banks x 1Mbit x 16. The
V54C365164VD(L) achieves high speed data trans-
fer rates up to 225 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
225 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T
Access Time (ns)
45 5
6
7
••• •
Power
Std. L
••
Temperature
Mark
Blank
V54C365164VD(L) Rev. 1.3 September 2001
1

1 Page





V54C365164VL pdf, ピン配列
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MOSEL VITELIC
56 Ball Grid Array (or BGA)
V54C365164VD(L)
WBGA SDRAM (X4/X8/X16) 56 PINS ASSIGNMENT (Top View)
X4
X8
NC VSS
NC VSSQ
VDDQ DQ3
NC NC
NC VSSQ
VDDQ DQ2
VSS NC
DQM NC
CKE CLK
A11
A8 A9
A6 A7
A4 A5
NC VSS
DQ7 VSS
NC VSSQ
VDDQ DQ6
DQ5 NC
NC VSSQ
VDDQ DQ4
VSS NC
DQM NC
CKE CLK
A11
A8 A9
A6 A7
A4 A5
NC VSS
DQ15 VSS
DQ14 VSSQ
VDDQ DQ13
DQ11 DQ12
DQ10 VSSQ
VDDQ DQ9
VSS DQ8
UDQM NC
CKE CLK
A11
A8 A9
A6 A7
A4 A5
NC VSS
X16
VDD NC
VDDQ DQ0
DQ2 DQ1
DQ3 VSSQ
VDDQ DQ4
DQ6 DQ5
DQ7 VSSQ
LDQM VDD
CAS WE
CS RAS
BA1 BA0
A0 A10
A2 A1
VDD A3
VDD NC
VDDQ DQ0
DQ1 NC
NC VSSQ
VDDQ DQ2
DQ3 NC
NC VSSQ
NC VDD
CAS WE
CS RAS
BA1 BA0
A0 A10
A2 A1
VDD A3
VDD NC
VDDQ NC
DQ1 NC
NC VSSQ
VDDQ NC
DQ1 NC
NC VSSQ
NC VDD
CAS WE
CS RAS
BA1 BA0
A0 A10
A2 A1
VDD A3
V54C365164VD(L) Rev. 1.3 September 2001
3


3Pages


V54C365164VL 電子部品, 半導体
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MOSEL VITELIC
V54C365164VD(L)
Signal Pin Description
Pin Type
CLK
Input
CKE
Input
CS Input
RAS, CAS Input
WE
A0 - A11 Input
Signal Polarity
Function
Pulse
Positive The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
Edge clock.
Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Level
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
4M x 16 SDRAM CA0CA7 (Page Length = 256 bits)
BA0,
BA1
DQx
DQM
LDQM
UDQM
Input
Input
Output
Input
VCC, VSS Supply
VCCQ
VSSQ
Supply
Level
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
Selects which bank is to be active.
Level
Data Input/Output pins operate in the same manner as on conventional DRAMs.
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
LDQM and UDQM controls the lower and upper bytes in a x16 SDRAMs.
Power and ground for the input buffers and the core logic.
— — Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V54C365164VD(L) Rev. 1.3 September 2001
6

6 Page



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部品番号部品説明メーカ
V54C365164VC

HIGH PERFORMANCE 166/143/125 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16

Mosel Vitelic Corp
Mosel Vitelic Corp
V54C365164VD

HIGH PERFORMANCE 225/200/166/143 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16

Mosel Vitelic
Mosel Vitelic
V54C365164VE

(V54C3xxxx4VE) 64Mbit SDRAM

ProMOS Technologies
ProMOS Technologies
V54C365164VL

HIGH PERFORMANCE 225/200/166/143 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16

Mosel Vitelic
Mosel Vitelic


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