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PDF GS84118AT Data sheet ( Hoja de datos )
| Número de pieza | GS84118AT | |
| Descripción | 256K x 18 Sync Cache Tag | |
| Fabricantes | GSI Technology | |
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GS84118AT/B-166/150/130/100
TQFP, BGA
Commercial Temp
Industrial Temp
256K x 18 Sync
Cache Tag
166 MHz–100 MHz
3.3 V VDD
3.3 V and 2.5 V I/O
Features
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
• LBO pin for Linear or Interleave (PentiumTM and X86) Burst
mode
• Synchronous address, data I/O, and control inputs
• Synchronous Data Enable (DE)
• Asynchronous Output Enable (OE)
• Asynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTAG Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP and 119-BGA packages
• Pb-Free 100-lead TQFP package available
Functional Description
The GS84118A is a 256K x 18 high performance synchronous
SRAM with integrated Tag RAM comparator. A 2-bit burst
counter is included to provide burst interface with PentiumTM
and other high performance CPUs. It is designed to be used as
a Cache Tag SRAM, as well as data SRAM. Addresses, data
IOs, match output, chip enables (CE1, CE2, CE3), address
control inputs (ADSP, ADSC, ADV), and write control inputs
(BW1, BW2, BWE, GW, DE) are synchronous and are
controlled by a positive-edge-triggered clock (CLK).
Output Enable (OE), Match Output Enable, and power down
control (ZZ) are asynchronous. Burst can be initiated with
either ADSP or ADSC inputs. Subsequent burst addresses are
generated internally and are controlled by ADV. The burst
sequence is either interleave order (PentiumTM or x86) or
linear order, and is controlled by LBO.
Output registers and the Match output register are provided and
controlled by the FT mode pin (Pin 14). Through use of the FT
mode pin, I/O registers can be programmed to perform pipeline
or flow through operation. Flow Through mode reduces
latency.
Byte write operation is performed by using Byte Write Enable
(BWE) input combined with two individual byte write signals
BW1-2. In addition, Global Write (GW) is available for
writing all bytes at one time.
Compare cycles begin as a read cycle with output disabled so
that compare data can be loaded into the data input register.
The comparator compares the read data with the registered
input data and a match signal is generated. The match output
can be either in Pipeline or Flow Through modes controlled by
the FT signal.
Low power (Standby mode) is attained through the assertion of
the ZZ signal, or by stopping the clock (CLK). Memory data is
retained during Standby mode.
JTAG boundary scan interface is provided using IEEE
standard 1149.1 protocol. Four pins—Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS)—are used to perform JTAG function.
The GS84118A operates on a 3.3 V power supply and all
inputs/outputs are 3.3 V or 2.5 V LVTTL-compatible.
Separate output (VDDQ) pins are used to allow both 3.3 V or
2.5 V IO interface.
* Pentium is a trademark of Intel Corp.
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Parameter Synopsis
-166 -150 -133
tcycle 6.0 ns 6.6 ns 7.5 ns
tKQ 3.5 ns 3.8 ns 4.0 ns
IDD 310 mA 275 mA 250 mA
tKQ 8.5 ns 10 ns 11 ns
tcycle 10 ns 10 ns 15 ns
IDD 190 mA 190 mA 140 mA
-100
10 ns
4.5 ns
190 mA
12 ns
15 ns
140 mA
Rev: 1.02 4/2005
1/20
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. * Pentium is a trademark of Intel
1 page  
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Functional Block Diagram
GS84118AT/B-166/150/130/100
18
A0–A17
REGISTER
DQ
A0
A1
LBO
ADV
CLK
ADSC
ADSP
D0 Q0
BINARY
D1 COUNTER Q1
Load
A0
A1
GW
BWE
Register
DQ
BW1
Register
DQ
BW2
DE
Register
DQ
CE1
CE2
CE3
ZZ
FT
OE
MOE
A, DQ,
Control
TDI
TMS
TCK
Powerdown
Control
54 Boundary Scan
Registers
Bypass Reg
ID Reg.
Instruction Reg.
TAP
Controller
Register
DQ
Register
DQ
TDO
18
A
256K X 18
Memory
Array
QD
18
2
18
18
DQ1–DQ16
DQP1–DQP2
Match
Rev: 1.02 4/2005
5/20
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
5 Page 
www.DataSheet4U.com
GS84118AT/B-166/150/130/100
Operating Currents
Parameter
Test Conditions
Operating
Current
Device Selected;
All other inputs
≥ VIH Or ≤ VIL
Output open
Standby Current ZZ ≥ VDD – 0.2 V
Deselect Supply
Current
Device Deselected;
All other inputs
≥ VIH OR ≤ VIL
Symbol
IDD
Pipeline
IDD
Flow Through
ISB
Pipeline
ISB
Flow Through
IDD
Pipeline
IDD
Flow Through
-166
0 –40
to to
70°C +85°C
310 320
190 200
30 40
30 40
110 120
80 90
-150
0 –40
to to
70°C +85°C
275 285
190 200
30 40
30 40
105 115
80 90
-133
0 –40
to to
70°C +85°C
250 260
140 150
30 40
30 40
100 110
65 75
-100
0 –40 Unit
to to
70°C +85°C
190 200 mA
140 150 mA
30 40 mA
30 40 mA
80 90 mA
65 75 mA
Rev: 1.02 4/2005
11/20
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
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