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I386のメーカーはIntelです、この部品の機能は「Programmers Reference Manual」です。 |
部品番号 | I386 |
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部品説明 | Programmers Reference Manual | ||
メーカ | Intel | ||
ロゴ | |||
このページの下部にプレビューとI386ダウンロード(pdfファイル)リンクがあります。 Total 30 pages
www.DataSheet4U.com
INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986
INTEL 80386
PROGRAMMER'S REFERENCE MANUAL
1986
Intel Corporation makes no warranty for the use of its products and
assumes no responsibility for any errors which may appear in this document
nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any
time, without notice.
Contact your local sales office to obtain the latest specifications before
placing your order.
The following are trademarks of Intel Corporation and may only be used to
identify Intel Products:
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, Genius, i, î,
ICE, iCEL, iCS, iDBP, iDIS, I²ICE, iLBX, im, iMDDX, iMMX, Inboard,
Insite, Intel, intel, intelBOS, Intel Certified, Intelevision,
inteligent Identifier, inteligent Programming, Intellec, Intellink,
iOSP, iPDS, iPSC, iRMK, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, Library
Manager, MAPNET, MCS, Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL,
MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP, PC BUBBLE, Plug-A-Bubble,
PROMPT, Promware, QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80,
RUPI, Seamless, SLD, SugarCube, SupportNET, UPI, and VLSiCEL, and the
combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a numerical
suffix, 4-SITE.
MDS is an ordering code only and is not used as a product name or
trademark. MDS(R) is a registered trademark of Mohawk Data Sciences
Corporation.
Additional copies of this manual or other Intel literature may be obtained
from:
Intel Corporation
Literature Distribution
Mail Stop SC6-59
3065 Bowers Avenue
Santa Clara, CA 95051
INTEL CORPORATION 1987 CG-5/26/87
Edited 2001-02-01 by G.N.
Page 1 of 421
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INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986
Training Center Locations
To obtain a complete catalog of our workshops, call the nearest Training
Center in your area.
Boston
Chicago
San Francisco
Washington D.C.
Isreal
Tokyo
Osaka (Call Tokyo)
Toronto, Canada
London
Munich
Paris
Stockholm
Milan
Benelux (Rotterdam)
Copenhagen
Hong Kong
(617) 692-1000
(312) 310-5700
(415) 940-7800
(301) 474-2878
(972) 349-491-099
03-437-6611
03-437-6611
(416) 675-2105
(0793) 696-000
(089) 5389-1
(01) 687-22-21
(468) 734-01-00
39-2-82-44-071
(10) 21-23-77
(1) 198-033
5-215311-7
Page 3 of 421
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INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986
5.2.3 Page Tables............................................................................................................................................ 99
5.2.4 Page-Table Entries ................................................................................................................................ 99
5.2.4.1 Page Frame Address ........................................................................................................................................ 100
5.2.4.2 Present Bit ....................................................................................................................................................... 100
5.2.4.3 Accessed and Dirty Bits .................................................................................................................................. 101
5.2.4.4 Read/Write and User/Supervisor Bits.............................................................................................................. 101
5.2.5 Page Translation Cache....................................................................................................................... 101
5.3 COMBINING SEGMENT AND PAGE TRANSLATION......................................................................................... 102
5.3.1 "Flat" Architecture............................................................................................................................... 102
5.3.2 Segments Spanning Several Pages....................................................................................................... 102
5.3.3 Pages Spanning Several Segments....................................................................................................... 103
5.3.4 Non-Aligned Page and Segment Boundaries ....................................................................................... 104
5.3.5 Aligned Page and Segment Boundaries ............................................................................................... 104
5.3.6 Page-Table per Segment ...................................................................................................................... 104
CHAPTER 6 PROTECTION ............................................................................................................................ 106
6.1 WHY PROTECTION? ..................................................................................................................................... 106
6.2 OVERVIEW OF 80386 PROTECTION MECHANISMS ....................................................................................... 106
6.3 SEGMENT-LEVEL PROTECTION .................................................................................................................... 107
6.3.1 Descriptors Store Protection Parameters ............................................................................................ 107
6.3.1.1 Type Checking ................................................................................................................................................ 109
6.3.1.2 Limit Checking................................................................................................................................................ 110
6.3.1.3 Privilege Levels ............................................................................................................................................... 112
6.3.2 Restricting Access to Data ................................................................................................................... 113
6.3.2.1 Accessing Data in Code Segments .................................................................................................................. 114
6.3.3 Restricting Control Transfers .............................................................................................................. 115
6.3.4 Gate Descriptors Guard Procedure Entry Points................................................................................ 116
6.3.4.1 Stack Switching............................................................................................................................................... 119
6.3.4.2 Returning from a Procedure ............................................................................................................................ 122
6.3.5 Some Instructions are Reserved for Operating System ........................................................................ 122
6.3.5.1 Privileged Instructions..................................................................................................................................... 123
6.3.5.2 Sensitive Instructions....................................................................................................................................... 124
6.3.6 Instructions for Pointer Validation ...................................................................................................... 124
6.3.6.1 Descriptor Validation ...................................................................................................................................... 125
6.3.6.2 Pointer Integrity and RPL................................................................................................................................ 126
6.4 PAGE-LEVEL PROTECTION........................................................................................................................... 126
6.4.1 Page-Table Entries Hold Protection Parameters ................................................................................ 126
6.4.1.1 Restricting Addressable Domain ..................................................................................................................... 127
6.4.1.2 Type Checking ................................................................................................................................................ 127
6.4.2 Combining Protection of Both Levels of Page Tables ......................................................................... 127
6.4.3 Overrides to Page Protection .............................................................................................................. 128
6.5 COMBINING PAGE AND SEGMENT PROTECTION ........................................................................................... 128
CHAPTER 7 MULTITASKING ....................................................................................................................... 130
7.1 TASK STATE SEGMENT ................................................................................................................................ 130
7.2 TSS DESCRIPTOR......................................................................................................................................... 133
7.3 TASK REGISTER ........................................................................................................................................... 134
7.4 TASK GATE DESCRIPTOR ............................................................................................................................. 135
7.5 TASK SWITCHING......................................................................................................................................... 137
7.6 TASK LINKING ............................................................................................................................................. 141
7.6.1 Busy Bit Prevents Loops ...................................................................................................................... 141
7.6.2 Modifying Task Linkages ..................................................................................................................... 142
7.7 TASK ADDRESS SPACE................................................................................................................................. 142
7.7.1 Task Linear-to-Physical Space Mapping ............................................................................................. 143
7.7.2 Task Logical Address Space ................................................................................................................ 143
CHAPTER 8 INPUT/OUTPUT ......................................................................................................................... 145
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部品番号 | 部品説明 | メーカ |
I386 | Programmers Reference Manual | Intel |