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GS8640V36T-xxx の電気的特性と機能

GS8640V36T-xxxのメーカーはGSI Technologyです、この部品の機能は「(GS8640VxxT-xxx) 4M x 18/ 2M x 32/ 2M x 36 72Mb Sync Burst SRAMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS8640V36T-xxx
部品説明 (GS8640VxxT-xxx) 4M x 18/ 2M x 32/ 2M x 36 72Mb Sync Burst SRAMs
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS8640V36T-xxx Datasheet, GS8640V36T-xxx PDF,ピン配置, 機能
www.DataSheet4U.com
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GS8640V18/32/36T-300/250/200/167
100-Pin TQFP
Commercial Temp
Industrial Temp
4M x 18, 2M x 32, 2M x 36
72Mb Sync Burst SRAMs
300 MHz167 MHz
1.8 V VDD
1.8 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 1.8 V +10%/10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS8640V18/32/36T is a 75,497,472-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8640V18/32/36T operates on a 1.8 V power supply. All
input are 1.8 V compatible. Separate output power (VDDQ)
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Parameter Synopsis
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-300 -250 -200 -167 Unit
2.3 2.5 3.0 3.5 ns
3.3 4.0 5.0 6.0 ns
400 340 290 260 mA
480 410 350 305 mA
5.5 6.5 7.5 8.0 ns
5.5 6.5 7.5 8.0 ns
285 245 220 210 mA
330 280 250 240 mA
Rev: 1.00 9/2004
1/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

1 Page





GS8640V36T-xxx pdf, ピン配列
www.DataSheet4U.com
Product Preview
GS8640V18/32/36T-300/250/200/167
GS8640V32 100-Pin TQFP Pinout (Package T)
NC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
2M x 32
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
NC
Rev: 1.00 9/2004
3/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology


3Pages


GS8640V36T-xxx 電子部品, 半導体
www.DataSheet4U.com
A0An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
Product Preview
GS8640V18/32/36T-300/250/200/167
GS8640V18/32/36 Block Diagram
D0 Q0
D1 Q1
Counter
Load
A0
A1
Register
DQ
Register
DQ
Register
DQ
Register
DQ
A
Memory
Array
QD
36
4
36
Register
DQ
E1
E2
E3
FT
G
ZZ Power Down
Control
Note: Only x36 version shown for simplicity.
Register
DQ
Register
DQ
DQx1DQx9
Rev: 1.00 9/2004
6/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

6 Page



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部品番号部品説明メーカ
GS8640V36T-xxx

(GS8640VxxT-xxx) 4M x 18/ 2M x 32/ 2M x 36 72Mb Sync Burst SRAMs

GSI Technology
GSI Technology


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