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V58C2512164SBのメーカーはProMOS Technologiesです、この部品の機能は「High Performance 512M-Bit DDR SDRAM」です。 |
部品番号 | V58C2512164SB |
| |
部品説明 | High Performance 512M-Bit DDR SDRAM | ||
メーカ | ProMOS Technologies | ||
ロゴ | |||
このページの下部にプレビューとV58C2512164SBダウンロード(pdfファイル)リンクがあります。 Total 61 pages
www.DataSheet4U.com
V58C2512(804/404/164)SB
HIGH PERFORMANCE 512 Mbit DDR SDRAM
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 8Mbit X 16 (164)
Clock Cycle Time (tCK2.5)
Clock Cycle Time (tCK3)
System Frequency (fCK max)
5
DDR400
6ns
5ns
200 MHz
6
DDR333
6ns
-
166 MHz
75
DDR266
7.5ns
-
133 MHz
Features
■ High speed data transfer rates with system frequency
up to 200MHz
■ Data Mask for Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2.5, 3
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8192 cycles/64 ms
■ Available in 60 Ball FBGA AND 66 Pin TSOP II
■ SSTL-2 Compatible I/Os
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■ Differential clock inputs CK and CK
■ Power Supply 2.5V ± 0.2V
■ Power Supply 2.6V ± 0.1V for DDR400
■ tRAS lockout supported
■ Concurrent auto precharge option is supported
*Note:
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-75) Supports PC2100 module with 2.5-3-3 timing
Description
The V58C2512(804/404/164)SB is a four bank DDR
DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x
32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The
V58C2512(804/404/164)SB achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 FBGA
•
V58C2512(804/404/164)SB Rev.1.4 March 2007
CK Cycle Time (ns)
-5 -6
••
1
-75
•
Power
Std.
•
L
•
Temperature
Mark
Blank
1 Page www.DataSheet4U.com
ProMOS TECHNOLOGIES
60-Ball FBGA PIN OUT
V58C2512(804/404/164)SB
(x4) 1
23
78
9 (x8) 1
23
78
9
VSSQ NC VSS A VDD NC VDDQ
NC VDDQ DQ3 B
DQ0 VSSQ NC
NC VSSQ NC C
NC VDDQ NC
NC VDDQ DQ2 D
DQ1 VSSQ NC
NC
VREF
VSSQ DQS
VSS DM
E
F
NC VDDQ NC
NC VDD
NC
CK CK G WE CAS
A12 CKE H RAS CS
A11 A9 J BA1 BA0
A8 A7 K A0 AP/A10
A6 A5 L A2 A1
A4 VSS M VDD A3
X4 Device Ball Pattern
VSSQ DQ7 VSS A VDD DQ0 VDDQ
NC VDDQ DQ6 B DQ1 VSSQ NC
NC VSSQ DQ5 C DQ2 VDDQ NC
NC VDDQ DQ4 D DQ3 VSSQ NC
NC
VREF
VSSQ
VSS
DQS
DM
E
F
NC VDDQ NC
NC VDD
NC
CK CK G WE CAS
A12 CKE H RAS CS
A11 A9 J BA1 BA0
A8
A7 K
A0 AP/A10
A6 A5 L A2 A1
A4 VSS M VDD A3
X8 Device Ball Pattern
(x16) 1
23
78
9
VSSQ DQ15 VSS A VDD DQ0 VDDQ
DQ14
DQ12
VDDQ
VSSQ
DQ13
DQ11
B
C
DQ2
DQ4
VSSQ
VDDQ
DQ1
DQ3
DQ10 VDDQ DQ9 D
DQ6 VSSQ DQ5
DQ8
VREF
VSSQ
VSS
UDQS E
UDM F
LDQS VDDQ
LDM VDD
DQ7
NC
CK CK G WE CAS
A12 CKE H RAS CS
A11 A9 J BA1 BA0
A8 A7 K A0 AP/A10
A6 A5 L A2 A1
A4
VSS M
VDD
A3
X16 Device Ball Pattern
PIN A1 INDEX
123
A
789
B
C
D
E
F
G
H
J
K
L
M
TOP VIEW
(See the ball through the package)
V58C2512(804/404/164)SB Rev. 1.4 March 2007
3
3Pages www.DataSheet4U.com
ProMOS TECHNOLOGIES
V58C2512(804/404/164)SB
Block Diagram
Column address
counter
128M x 4
Column Addresses
A0 - A9, A11, A12, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
8192 x 4096
Row decoder
Memory array
Bank 1
8192 x 4096
Row decoder
Memory array
Bank 2
8192 x 4096
Row decoder
Memory array
Bank 3
8192 x 4096
CK, CK
DQS
Input buffer Output buffer
DLL
Strobe
Gen.
DQ0-DQ3
Data Strobe
Control logic & timing generator
V58C2512(804/404/164)SB Rev. 1.4 March 2007
6
6 Page | |||
ページ | 合計 : 61 ページ | ||
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
V58C2512164SB | High Performance 512M-Bit DDR SDRAM | ProMOS Technologies |
V58C2512164SBI5 | High Performance 512M-Bit DDR SDRAM | ProMOS Technologies |