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S2042 の電気的特性と機能

S2042のメーカーはAMCCです、この部品の機能は「(S2042 / S2043) HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS」です。


製品の詳細 ( Datasheet PDF )

部品番号 S2042
部品説明 (S2042 / S2043) HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
メーカ AMCC
ロゴ AMCC ロゴ 




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S2042 Datasheet, S2042 PDF,ピン配置, 機能
www.DataSheet4U.com
PRELIMINARY
DHEIVGICHEPSEPERCFIOFIRCAMTAIONNCE SERIAL INTERFACE CIRCUITS
BHiICGMHOPSERPFEOCRLMCALNOCCEK SGEERNIAERLAINTTOERRFACE CIRCUITS
®
S2042/S2043
S2042/S2043
FEATURES
• Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards
• S2042 transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
reference
• S2043 receiver PLL configured for clock and
data recovery
• 1062, 531 and 266 Mb/s operation
• 10- or 20-bit parallel TTL compatible interface
• 1 watt typical power dissipation for chipset
• +3.3/+5V power supply
• Low-jitter serial PECL compatible interface
• Lock detect
• Local loopback
• 10mm x 10mm 52 PQFP package
• Fibre Channel framing performed by receiver
• Continuous downstream clocking from receiver
• TTL compatible outputs possible with +5V I/O
power supply
APPLICATIONS
High-speed data communications
• Supercomputer/Mainframe
• Workstation
• Switched networks
• Proprietary extended backplanes
• Mass storage devices/RAID drives
GENERAL DESCRIPTION
The S2042 and S2043 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the ANSI X3T11
Fibre Channel specification. The chipset is select-
able to 1062, 531 or 266 Mbit/s data rates with
associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2042 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2043
on-chip PLL synchronizes directly to incoming digital
signals to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Lo-
cal loopback allows for system diagnostics. The TTL
I/O section can operate from either a +3.3V or a +5V
power supply. With a 3.3V power supply the chipset
dissipates only 1W typically.
Figure 1 shows a typical network configuration incor-
porating the chipset. The chipset is compatible with
AMCC’s S2036 Open Fiber Control (OFC) device.
Figure 1. System Block Diagram
S2036
Open
Fiber
Control
(OFC)
Fibre
Channel
Controller
S2042
TX
S2043
RX
Optical
TX
Optical
RX
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Optical
RX
Optical
TX
S2043
RX
S2042
TX
S2036
Open
Fiber
Control
(OFC)
Fibre
Channel
Controller
1

1 Page





S2042 pdf, ピン配列
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2043
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit or 20-
bit wide data from the input latch and converts it to a
serial data stream. Parallel data is latched into the
transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10 times the REFCLK
input frequency. The state of the serial outputs is
controlled by the output enable pins, OE0 and OE1.
D10 is transmitted first in 10-bit mode. D0 is trans-
mitted first in 20-bit mode. Table 2 shows the mapping
of the parallel data to the 8B/10B codes.
10-Bit/20-Bit Mode
The S2042 operates with either 10-bit or 20-bit par-
allel data inputs. Word width is selectable via the
DWS pin. In 10-bit mode, D10–D19 are used and
D0–D9 are ignored.
Reference Clock Input
The reference clock input (REFCLK) must be sup-
plied with a single-ended AC coupled crystal clock
source with 100 PPM tolerance to assure that the
transmitted data meets the Fibre Channel frequency
limits. The internal serial clock is frequency locked to
the reference clock. The word rate clock (TCLK, TCLKN)
output frequency is determined by the selected oper-
ating speed and word width. Refer to Table 1 for
TCLK/TCLKN clock frequencies.
Table 1. Transmitter Operating Modes
Reference
Word Clock TCLK/TCLKN
Data Rate Width Frequency Frequency
RATESEL DWS REFSEL (Mbits/sec) (Bits) (MHz)
(MHz)
0
1
1
1062.5
10 106.25
53.125
0
0
0
1062.5
20 53.125
53.125
1
1
1
531.25
10 53.125
53.125
1
0
0
531.25
20 26.5625
26.5625
Open 1
1 265.625 10 26.5625 26.5625
Table 2. Data Mapping to 8b/10b Alphabetic Representation
TX[00:19] or
RX[00:19]
8b/10b alphabetic
representation
First Data Byte
Second Data Byte
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
abcdei f ghj abcdei f ghj
First bit transmitted in 20-bit mode
First bit transmitted in 10-bit mode
Figure 4. S2043 Functional Block Diagram
LOCK_REF
RATESEL
REFCLK
REFSEL
RX
RY
RLX
RLY
LPEN
SYNCEN
DWS
2:1
CONTROL
LOGIC
D SHIFT
REGISTER
PLL CLOCK
RECOVERY
BITCLK
LOCKDETN
20
DQ
D(0..19)
SYNC
DETECT
LOGIC
SYNC
RCLK
RCLKN
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
3


3Pages


S2042 電子部品, 半導体
S2042/S2043
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042 Pin Assignment and Descriptions
Pin Name Level I/O Pin # Description
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TEST
DWS
REFCLK
TCLK
TCLKN
TTL I
Static
Multi-
Level
TTL
TTL
I
I
PECL
I
Diff. O
TTL
50 Accepts parallel input data. Data is clocked in on the rising edge
49 of REFCLK. In 20-bit mode, D0 is transmitted first. In 10-bit
48 mode, D10-19 are used, D0-D9 are ignored, and D10 is
47 transmitted first.
44
43
42
41
38
37
36
35
31
30
29
28
25
24
23
22
20 Multilevel input used for factory testing. When not connected,
REFCLK replaces the internal bit clock to facilitate factory
testing. In normal use, this input is wired to ground.
19 The level on this pin selects the parallel data bus width. When
LOW, a 20-bit parallel bus width is selected, and D(0-19) are
active. When HIGH, a 10-bit parallel data bus is selected, D(10-
19) are active and D(0-9) are not used. (See Table 1.) A rising
edge will reset the part (used for test).
16 (Externally capacitively coupled.) A crystal-controlled reference
clock for the PLL clock multiplier. The frequency of REFCLK is
set by the REFSEL pin. (See Table 1.)
12 Differential TTL word rate clock true and complement. See
11 Table 1 for frequency.
TY
Diff. O
9 Differential PECL outputs that transmit the serial data and drive
TX PECL 8 75W or 50W termination to Vcc-2V. Enabled by OE0. TX is the
positive output, and TY is the negative output.
TLX
Diff. O
5 Differential PECL outputs that are functionally equivalent to TX
TLY PECL
4 and TY. They are intended to be used for loopback testing.
Enabled by OE1.
Applied Micro Circuits Corporation
6 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333

6 Page



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