DataSheet.jp

GS74116TU の電気的特性と機能

GS74116TUのメーカーはGSI Technologyです、この部品の機能は「256K x 16 4Mb Asynchronous SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS74116TU
部品説明 256K x 16 4Mb Asynchronous SRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




このページの下部にプレビューとGS74116TUダウンロード(pdfファイル)リンクがあります。
Total 14 pages

No Preview Available !

GS74116TU Datasheet, GS74116TU PDF,ピン配置, 機能
www.DataSheet4U.com
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
256K x 16
4Mb Asynchronous SRAM
GS74116TP/J/U
8, 10, 12, 15ns
3.3V VDD
Center VDD & VSS
Features
• Fast access time: 8, 10, 12, 15ns
• CMOS low power operation: 170/145/130/110 mA at min.cycle time.
• Single 3.3V ± 0.3V power supply
• All inputs and outputs are TTL compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: -40° to 85°C
• Package line up
J: 400mil, 44 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package
U: 7.20mm x 11.65mm Fine Pitch Ball Grid Array package
Description
The GS74116 is a high speed CMOS static RAM organized as
262,144-words by 16-bits. Static design eliminates the need for exter-
nal clocks or timing strobes. Operating on a single 3.3V power supply
and all inputs and outputs are TTL compatible. The GS74116 is avail-
able in a 7.2x11.65 mm Fine Pitch BGA package, 400 mil SOJ and
400 mil TSOP Type-II packages.
Pin Descriptions
Symbol
A0 to A17
DQ1 to DQ16
CE
LB
UB
WE
OE
VDD
VSS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3V power supply
Ground
No connect
SOJ 256K x 16 Pin Configuration
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
Top view
DQ1 7
DQ2 8
DQ3 9
DQ4 10
VDD 11
44 pin
VSS 12
DQ5 13
SOJ
DQ6 14
DQ7 15
DQ8 16
WE 17
A15 18
A14 19
A13 20
A12 21
A16 22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ16
DQ15
DQ14
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
A17
Fine Pitch BGA 256K x 16 Bump Configuration
123456
A LB OE A0 A1 A2 NC
B DQ16 UB A3 A4 CE DQ1
C DQ14 DQ15 A5 A6 DQ2 DQ3
D VSS DQ13 A17 A7 DQ4 VDD
E VDD DQ12 NC A16 DQ5 VSS
F DQ11 DQ10 A8 A9 DQ7 DQ6
G DQ9 NC A10 A11 WE DQ8
H NC A12 A13 A14 A15 NC
7.2x11.65mm 0.75mm Bump Pitch
Top View
Rev: 2.02 3/2000
1/14
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
N

1 Page





GS74116TU pdf, ピン配列
GS74116TP/J/U
Truth Table
CE OE WE LB UB
HXXXX
LL
L LHLH
HL
LL
LXL LH
HL
L HH X X
L XXHH
Note: X: “H” or “L”
DQ1 to DQ8
Not Selected
Read
Read
High Z
Write
Write
Not Write, High Z
High Z
High Z
DQ9 to DQ16
Not Selected
Read
High Z
Read
Write
Not Write, High Z
Write
High Z
High Z
VDD Current
ISB1, ISB2
IDD
Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Output Voltage
Allowable power dissipation
Storage temperature
Symbol
VDD
VIN
VOUT
PD
TSTG
Rating
-0.5 to +4.6
-0.5 to VDD+0.5
(4.6V max.)
-0.5 to VDD+0.5
(4.6V max.)
0.7
-55 to 150
Unit
V
V
V
W
oC
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 2.02 3/2000
3/14
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
N


3Pages


GS74116TU 電子部品, 半導体
AC Characteristics
GS74116TP/J/U
Read Cycle
Parameter
Symbol
Read cycle time
Address access time
Chip enable access time (CE)
Byte enable access time (UB, LB)
Output enable to output valid (OE)
Output hold from address change
tRC
tAA
tAC
tAB
tOE
tOH
Chip enable to output in low Z (CE)
tLZ*
Output enable to output in low Z (OE)
tOLZ*
Byte enable to output in low Z (UB, LB)
tBLZ*
Chip disable to output in High Z (CE)
tHZ*
Output disable to output in High Z (OE)
tOHZ*
Byte disable to output in High Z (UB, LB)
tBHZ*
* These parameters are sampled and are not 100% tested
-8
Min Max
8 ---
--- 8
--- 8
--- 3.5
--- 3.5
3 ---
3 ---
0 ---
0 ---
--- 4
--- 3.5
--- 3.5
-10
Min Max
10 ---
--- 10
--- 10
--- 4
--- 4
3 ---
3 ---
0 ---
0 ---
--- 5
--- 4
--- 4
-12
Min Max
12 ---
--- 12
--- 12
--- 5
--- 5
3 ---
3 ---
0 ---
0 ---
--- 6
--- 5
--- 5
-15
Min Max
15 ---
--- 15
--- 15
--- 6
--- 6
3 ---
3 ---
0 ---
0 ---
--- 7
--- 6
--- 6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL
Address
Data Out
tOH
Previous Data
tRC
tAA
Data valid
Rev: 2.02 3/2000
6/14
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
N

6 Page



ページ 合計 : 14 ページ
 
PDF
ダウンロード
[ GS74116TU データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
GS74116TJ

256K x 16 4Mb Asynchronous SRAM

GSI Technology
GSI Technology
GS74116TP

256K x 16 4Mb Asynchronous SRAM

GSI Technology
GSI Technology
GS74116TU

256K x 16 4Mb Asynchronous SRAM

GSI Technology
GSI Technology


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap