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PDF GS1540 Data sheet ( Hoja de datos )
| Número de pieza | GS1540 | |
| Descripción | HDTV Serial Digital Non-Equalizing Receiver | |
| Fabricantes | Gennum Corporation | |
| Logotipo |  |
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FEATURES
• SMPTE 292M compliant
• 1.485 and 1.485/1.001Gb/s operation
• integrated adjustment-free reclocker
• 1:20 serial to parallel conversion
• selectable reclocked serial output
• reclocker BYPASS capability
• LOCK detect
• input jitter indicator (IJI)
• 20 bit output
• 74.25MHz or 74.25/1.001MHz clock output
• single +5.0V power supply
• minimal component count for HD SDI receive
solutions
APPLICATIONS
SMPTE 292M Serial Digital Interfaces for Production
Switchers, Master Control Switchers, NLE's, and VTR's.
HD-LINX™ GS1540
HDTV Serial Digital
Non-Equalizing Receiver
PRELIMINARY DATA SHEET
DESCRIPTION
The GS1540 is a high performance integrated Receiver
designed for HDTV component signals, conforming to the
SMPTE 292M standard. The GS1540 includes adjustment
free clock and data recovery, and 1:20 serial to parallel
conversion.
The Clock and Data Recovery stage was designed to
automatically recover the embedded clock signal and
retime the data from SMPTE 292M compliant digital video
signals. There is also a selectable reclocked serial data
buffer output and the ability to bypass the reclocker stage.
A unique feature, Input Jitter Indicator (IJI), is included for
robust system design. This feature is used to indicate
excessive input jitter before the chip mutes the outputs.
The Serial to Parallel conversion stage provides 1:20 S/P
conversion.
The GS1540 uses the GO1515 external VCO connected to
the internal PLL circuitry to achieve ultra low noise PLL
performance.
ORDERING INFORMATION
PART NUMBER
PACKAGE
GS1540-CQR
128 pin MQFP
TEMPERATURE
0°C to 70°C
DDI
(opt) DDI_VTT
DDI
BUFFER1
SDOint
SDOint
RECLOCKER
CORE
S/P CONVERTER
BUFFER2
SDO_EN
SIMPLIFIED BLOCK DIAGRAM
DATA_OUT[19:0]
PCLK_OUT
SDO
SDO
Revision Date: August 2000
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
Document No. 522 - 27- 00
1 page  
NC
NC
BYPASS
DDI_VTT
NC
DDI
DDI
PD_VCC
NC
PDSUB_VEE
PD_VEE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64 DATA_OUT[19]
63 DATA_OUT[18]
62 DATA_OUT[17]
61 DATA_OUT[16]
60 DATA_OUT[15]
59 DATA_OUT[14]
58 NC
57 NC
56 DATA_OUT[13]
55 DATA_OUT[12]
54 DATA_OUT[11]
53 DATA_OUT[10]
52 NC
51 NC
50 DATA_OUT[9]
49 DATA_OUT[8]
48 DATA_OUT[7]
47 DATA_OUT[6]
46 DATA_OUT[5]
45 DATA_OUT[4]
44 DATA_OUT[3]
43 DATA_OUT[2]
42 DATA_OUT[1]
41 DATA_OUT[0]
40 NC
39 NC
5 Page 
Because most of the PLL circuitry is digital, it is more like
other digital systems which are generally more robust than
their analog counterparts. Additionally, signals like DM/DM
which represent the internal functionality can be generated
without adding additional artifacts. Thus, system debugging
is also possible with these features. The complete slew PLL
is made up of several blocks including the phase detector,
the charge pump and an external Voltage Controlled
Oscillator (VCO).
DIGITAL INPUT BUFFER
The input buffer is a self-biased circuit. On-chip 50Ω
termination resistors provide a seamless interface for other
HD-LINX™ products such as the GS1504 Adaptive Cable
Equalizer.
PHASE DETECTOR
The phase detector portion of the slew PLL used in the
GS1540 is a bi-level digital phase detector. It indicates
whether the data transition occurred before or after with
respect to the falling edge of the internal clock. When the
phase detector is locked, the data transition edges are
aligned to the falling edge of the clock. The input data is
then sampled by the rising edge of the clock, as shown in
Figure 17. In this manner, the allowed input jitter is 1UI p-p
in an ideal situation. However, due to setup and hold time,
the GS1540 typically achieves 0.5UI p-p input jitter
tolerance without causing any errors in this block. When the
signal is locked to the internal clock, the control output from
the phase detector is refreshed at the transition of each
rising edge of the data input. During this time, the phase of
the clock drifts in one direction.
PHASE ALIGNMENT
EDGE
IN-PHASE CLOCK
RE-TIMING
EDGE
INPUT DATA
WITH JITTER
0.5UI
CHARGE PUMP
The charge pump in a slew PLL is different from the charge
pump in a linear PLL. There are two main functions of the
charge pump. One function is to hold the frequency
information of the input data. This information is held by
CCP1, which is connected between LFS and LFS. The other
capacitor, CCP2 between LFS and LFA_GND is used to
remove common mode noise. Both CCP1 and CCP2 should
be the same value. The second function of the charge
pump is to provide a binary control voltage to the VCO
depending upon the phase detector output. The output pin,
LFA controls the VCO. Internally there is a 500Ω pull-up
resistor, which is driven with a 100µA current called ΙP.
Another analog current ΙF, with 5mA maximum drive
proportional to the voltage across the CCP1, is applied at the
same node. The voltage at the LFA node is
VLFA_VCC - 500(ΙP+ΙF) at any time.
Because of the integrator, ΙF changes very slowly whereas
ΙP could change at the positive edge of the data transition
as often as a clock period. In the locked position, the
average voltage at the LFA (VLFA_VCC – 500(ΙP/2+ΙF) is such
that VCO generates frequency ƒ, equal to the data rate
clock frequency. Since ΙP is changing all the time between
0A and 100µA, there will be two levels generated at the LFA
output.
VCO
The GO1515 is an external hybrid VCO, which has a centre
frequency of 1.485GHz and is also guaranteed to provide
1.485/1.001GHz within the control voltage (3.1V – 4.65V) of
the GS1540 over process, power supply and temperature.
The GO1515 is a very clean frequency source and,
because of the internal high Q resonator, it is an order of
magnitude more immune to external noise as compared to
on-chip VCOs.
The VCO gain, Kƒ, is nominally 16MHz/V. The control
voltage around the average LFA voltage will be 500 x ΙP/2.
This will produce two frequencies off from the centre by
ƒ=Kƒ x 500 x ΙP/2.
OUTPUT DATA
Fig. 17 Phase Detector Characteristics
During pathological signals, the amount of jitter that the
phase detector will add can be calculated. By choosing the
proper loop bandwidth, the amount of phase detector
induced jitter can also be limited. Typically, for a 1.41MHz
loop bandwidth at 0.2UI input jitter modulation, the phase
detector induced jitter is about 0.015UIp-p. This is not very
significant, even for the pathological signals.
LBCONT
The LBCONT pin is used to adjust the loop bandwidth by
externally changing the internal charge pump current. For
maximum loop bandwidth, connect LBCONT to the most
positive power supply. For medium loop bandwidth,
connect LBCONT through a pull-up resistor (RPULL-UP). For
low loop bandwidth, leave LBCONT floating. The formula
below shows the loop bandwidth for various configurations.
LBW = LBWNOMINAL × (--(-2--5-5--k--k--Ω-Ω-----+-+----R-R---P--P-U--U--L--L-L-L---–-–--U--U--P-P--)--)
where LBW nominal is the loop bandwidth when LBCONT is
left floating.
GENNUM CORPORATION
11
522 - 27- 00
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet GS1540.PDF ] | |
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